Simulation Results: keymgr

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.96 %
  • code
  • 98.99 %
  • assert
  • 97.72 %
  • func
  • 91.18 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.16 %
  • toggle
  • 98.60 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.48%
V2S
98.96%
V3
68.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 28.590s 2556.194us 50 50 100.00
random 50 50 100.00
keymgr_random 65.160s 34793.855us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.390s 38.369us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 24.740s 1234.294us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 10.750s 751.104us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.090s 47.215us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
keymgr_csr_aliasing 10.750s 751.104us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 88.640s 24688.755us 49 50 98.00
sideload 200 200 100.00
keymgr_sideload 29.240s 6141.619us 50 50 100.00
keymgr_sideload_kmac 27.090s 25966.795us 50 50 100.00
keymgr_sideload_aes 41.750s 3282.533us 50 50 100.00
keymgr_sideload_otbn 41.460s 3273.778us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 23.270s 3865.755us 50 50 100.00
lc_disable 47 50 94.00
keymgr_lc_disable 8.600s 709.363us 47 50 94.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 6.460s 224.856us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 55.860s 7625.099us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 11.550s 4460.276us 50 50 100.00
sync_async_fault_cross 50 50 100.00
keymgr_sync_async_fault_cross 27.020s 7597.013us 50 50 100.00
stress_all 50 50 100.00
keymgr_stress_all 240.460s 28642.570us 50 50 100.00
intr_test 50 50 100.00
keymgr_intr_test 1.260s 53.795us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.380s 74.561us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 5.860s 604.674us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 5.860s 604.674us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.390s 38.369us 5 5 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
keymgr_csr_aliasing 10.750s 751.104us 5 5 100.00
keymgr_same_csr_outstanding 4.160s 1509.471us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.390s 38.369us 5 5 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
keymgr_csr_aliasing 10.750s 751.104us 5 5 100.00
keymgr_same_csr_outstanding 4.160s 1509.471us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
keymgr_tl_intg_err 9.710s 262.293us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 7.200s 347.767us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 7.200s 347.767us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 7.200s 347.767us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 7.200s 347.767us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 15.710s 6151.005us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 9.710s 262.293us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 7.200s 347.767us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 88.640s 24688.755us 49 50 98.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 65.160s 34793.855us 50 50 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 65.160s 34793.855us 50 50 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 65.160s 34793.855us 50 50 100.00
keymgr_csr_rw 1.930s 95.031us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 47 50 94.00
keymgr_lc_disable 8.600s 709.363us 47 50 94.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 11.550s 4460.276us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 11.550s 4460.276us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 65.160s 34793.855us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 20.060s 4696.247us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 25.470s 1509.790us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 47 50 94.00
keymgr_lc_disable 8.600s 709.363us 47 50 94.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 25.470s 1509.790us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 25.470s 1509.790us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 25.470s 1509.790us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 16.490s 1521.578us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 25.470s 1509.790us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 34 50 68.00
keymgr_stress_all_with_rand_reset 22.740s 2246.478us 34 50 68.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 15 test runs
keymgr_stress_all_with_rand_reset 84810732935167831835799710336618335827786338593705020354287178544689494408983 915
UVM_INFO @ 1063282075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 71711993131655965910668459568186095532174291402523348986944840454537903457992 686
UVM_INFO @ 247887577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64274715553315504809199411841586998446306268960623957234138579504044546845771 106
UVM_INFO @ 307576266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 68849235566110347377113895401242857408598673018797938690054283207966453276530 928
UVM_INFO @ 1359215722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 78665899559409610312277527806865717359985177288287937617739459589029491904030 393
UVM_INFO @ 256583787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19849000310839489855062182410528305869479550133111760090078936360917524231566 97
UVM_INFO @ 243187199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 99723168871539276255898385543336676451505811898426841176844229954150765351471 446
UVM_INFO @ 173348361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 61366082045337152111428240180020864575432611998143276955526917822542798071148 322
UVM_INFO @ 150294041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 86088008450655340509122268790289331260313289272332058910156868500204784652838 280
UVM_INFO @ 464506141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 19326582007658809974022731399223129181859010460832729765338742865300870251397 369
UVM_INFO @ 172748802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 80715475540906282746420129132673337220137032499811115618120286943121838618545 410
UVM_INFO @ 538564526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 110392446048202643577267258297427576742591260568618160360535403759629451857074 310
UVM_INFO @ 139329400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 90198900046103083882710612846070151000135533536229028935191796636412911173356 1068
UVM_INFO @ 1492367757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 37663228165949850621884819482116873668911387040628438111537129280304966989942 416
UVM_INFO @ 141974330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 98048285314071272353979024672817160998428391601230663194254798608928545224163 235
UVM_INFO @ 810210017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 3 test runs
keymgr_lc_disable 67590379084438068739157203769470484974876730646328935422494152233136769089709 205
UVM_INFO @ 37635531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_cfg_regwen 57037769246751895299447404874724579636136338728711273197689729685727635260909 480
UVM_INFO @ 98056451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 62433613266831081534831866107676978008734898586291491571107334760742078762594 416
UVM_INFO @ 208256060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac 1 test run
keymgr_lc_disable 47511019105161271022384891705255283723378742603624182378739467030134258165744 657
UVM_INFO @ 141758629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) 1 test run
keymgr_lc_disable 113745854450457687002725790462315455900299705915489309233661896928220529384130 346
UVM_INFO @ 38113891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---