Simulation Results: kmac/masked

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 94.39 %
  • assert
  • 97.98 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.76 %
  • toggle
  • 99.89 %
  • FSM
  • 80.99 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.56%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 79.130s 15145.770us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.480s 88.743us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.590s 34.780us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 24.620s 2931.086us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.480s 766.264us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.070s 35.384us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.590s 34.780us 20 20 100.00
kmac_csr_aliasing 8.480s 766.264us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.120s 19.554us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.820s 23.176us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 5074.050s 142638.460us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1423.680s 139533.044us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2236.810s 123299.297us 5 5 100.00
kmac_test_vectors_sha3_256 2535.890s 186967.889us 5 5 100.00
kmac_test_vectors_sha3_384 1909.990s 80407.186us 5 5 100.00
kmac_test_vectors_sha3_512 1327.770s 188820.914us 5 5 100.00
kmac_test_vectors_shake_128 3042.930s 423177.371us 5 5 100.00
kmac_test_vectors_shake_256 2573.020s 351860.995us 5 5 100.00
kmac_test_vectors_kmac 3.920s 940.395us 5 5 100.00
kmac_test_vectors_kmac_xof 3.600s 227.512us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 443.190s 28388.707us 50 50 100.00
app 50 50 100.00
kmac_app 350.930s 17561.875us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 283.990s 18246.248us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 395.500s 73492.189us 50 50 100.00
error 50 50 100.00
kmac_error 427.860s 22373.300us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 17.080s 4100.385us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.060s 964.228us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 29.920s 3825.726us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 39.790s 1725.610us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 78.990s 8032.143us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 34.180s 802.294us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3316.510s 129375.618us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.210s 23.741us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.260s 82.440us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.260s 164.736us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.260s 164.736us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.480s 88.743us 5 5 100.00
kmac_csr_rw 1.590s 34.780us 20 20 100.00
kmac_csr_aliasing 8.480s 766.264us 5 5 100.00
kmac_same_csr_outstanding 3.180s 215.436us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.480s 88.743us 5 5 100.00
kmac_csr_rw 1.590s 34.780us 20 20 100.00
kmac_csr_aliasing 8.480s 766.264us 5 5 100.00
kmac_same_csr_outstanding 3.180s 215.436us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.840s 335.108us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.840s 335.108us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.840s 335.108us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.840s 335.108us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 6.540s 2254.181us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 80.310s 16981.557us 5 5 100.00
kmac_tl_intg_err 5.440s 194.106us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.440s 194.106us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 34.180s 802.294us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 79.130s 15145.770us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 443.190s 28388.707us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.840s 335.108us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 80.310s 16981.557us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 80.310s 16981.557us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 80.310s 16981.557us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 79.130s 15145.770us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 34.180s 802.294us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 80.310s 16981.557us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 354.390s 151841.390us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 79.130s 15145.770us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 242.000s 22187.482us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 108207810623389529496409100866852488321547426945009905085520840385056989696309 254
UVM_INFO @ 4209450436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 39596739768119777312987902994056897854641848821251633498925655246496240385121 275
UVM_INFO @ 3503929263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 88625357606734600659702958378651887887478927299672021078605511785251703054561 341
UVM_INFO @ 44917150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---