Simulation Results: kmac/unmasked

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.56 %
  • code
  • 92.53 %
  • assert
  • 97.90 %
  • func
  • 96.25 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.71 %
  • toggle
  • 100.00 %
  • FSM
  • 74.38 %
Validation stages
V1
100.00%
V2
98.31%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 66.820s 11769.965us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.390s 39.746us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.500s 95.707us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 20.940s 1419.269us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 6.860s 397.316us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 2.930s 71.059us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.500s 95.707us 20 20 100.00
kmac_csr_aliasing 6.860s 397.316us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.100s 21.090us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.930s 44.338us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4665.740s 138352.598us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 851.190s 35830.089us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2211.560s 321068.025us 5 5 100.00
kmac_test_vectors_sha3_256 1937.890s 66828.430us 5 5 100.00
kmac_test_vectors_sha3_384 1573.780s 265409.338us 5 5 100.00
kmac_test_vectors_sha3_512 1031.990s 49919.862us 5 5 100.00
kmac_test_vectors_shake_128 3007.480s 111242.124us 5 5 100.00
kmac_test_vectors_shake_256 1970.010s 75727.489us 5 5 100.00
kmac_test_vectors_kmac 3.220s 562.308us 5 5 100.00
kmac_test_vectors_kmac_xof 2.920s 80.410us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 427.840s 161195.532us 50 50 100.00
app 50 50 100.00
kmac_app 279.940s 14844.330us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 317.070s 38215.539us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 341.600s 179446.094us 50 50 100.00
error 50 50 100.00
kmac_error 393.770s 22303.772us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 14.020s 6948.841us 50 50 100.00
sideload_invalid 37 50 74.00
kmac_sideload_invalid 104.970s 10008.660us 37 50 74.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 36.370s 1456.551us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 42.380s 1580.729us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 65.950s 19114.822us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 18.740s 3634.889us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2405.150s 107420.273us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.190s 131.430us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.240s 179.541us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.580s 347.844us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.580s 347.844us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.390s 39.746us 5 5 100.00
kmac_csr_rw 1.500s 95.707us 20 20 100.00
kmac_csr_aliasing 6.860s 397.316us 5 5 100.00
kmac_same_csr_outstanding 3.670s 2233.847us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.390s 39.746us 5 5 100.00
kmac_csr_rw 1.500s 95.707us 20 20 100.00
kmac_csr_aliasing 6.860s 397.316us 5 5 100.00
kmac_same_csr_outstanding 3.670s 2233.847us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.800s 658.807us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.800s 658.807us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.800s 658.807us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.800s 658.807us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.430s 920.366us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 50.430s 33892.270us 5 5 100.00
kmac_tl_intg_err 6.260s 2366.220us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.260s 2366.220us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 18.740s 3634.889us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 66.820s 11769.965us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 427.840s 161195.532us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.800s 658.807us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 50.430s 33892.270us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 50.430s 33892.270us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 50.430s 33892.270us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 66.820s 11769.965us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 18.740s 3634.889us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 50.430s 33892.270us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 236.070s 7382.757us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 66.820s 11769.965us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 548.080s 25954.782us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 2 test runs
kmac_sideload_invalid 115203535148571513961995632066122554606544837751419516966639122639465943463017 78
UVM_INFO @ 10008660304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 17668297792587960563150509484105715746263692867852953985547518631774883618468 78
UVM_INFO @ 10032453055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
kmac_sideload_invalid 63302680433687403005671877325849117401879071211004059033833220810705518435308 88
UVM_INFO @ 10185053226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) 1 test run
kmac_sideload_invalid 98141159410280189889754791304848649302344320048490841386986075842980034571951 104
UVM_INFO @ 10716041736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
kmac_stress_all_with_rand_reset 99641625706031677058390765480444319236539492386855977175313606089203708318491 187
UVM_INFO @ 39774728172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
kmac_sideload_invalid 56447279678994197263540158007078376687628676102370245581929689112019285476599 85
UVM_INFO @ 10098136361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) 1 test run
kmac_sideload_invalid 53992195357916480835476060144580800309522170530502222417143922775555232863649 91
UVM_INFO @ 10490108214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) 1 test run
kmac_sideload_invalid 106221066976157150911617606507879969725825687769725153467944680009872537122669 102
UVM_INFO @ 10775176293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
kmac_sideload_invalid 111272639194206386126847755001243889432372777521269760503074371084029501484469 82
UVM_INFO @ 10059278197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) 1 test run
kmac_sideload_invalid 101464878297661164928004651942370525520232093187934869473636913620811997432331 93
UVM_INFO @ 10529968529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) 1 test run
kmac_sideload_invalid 41620835321016556343982426453277817166036770448637984938000707782911798957190 92
UVM_INFO @ 10105445195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) 1 test run
kmac_sideload_invalid 77670949628911571338632847138180030910505059745882069800006927768522695894646 85
UVM_INFO @ 10177716315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
kmac_sideload_invalid 41391302553234001495525704654718462691460332756650938124371188168542753698342 80
UVM_INFO @ 10410984583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) 1 test run
kmac_sideload_invalid 67221565190764412828729514175113605326198710321027355356270537228478727845740 81
UVM_INFO @ 10081355041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---