Simulation Results: lc_ctrl/volatile_unlock_enabled

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.27 %
  • code
  • 86.42 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.24 %
  • cond
  • 81.90 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 8.850s 4471.400us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.250s 27.190us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.290s 16.704us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 2.340s 53.279us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.340s 16.314us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.090s 84.421us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.290s 16.704us 20 20 100.00
lc_ctrl_csr_aliasing 1.340s 16.314us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 8.360s 492.631us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 15.980s 693.239us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.200s 18.317us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 4.200s 127.320us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_errors 48 50 96.00
lc_ctrl_errors 12.980s 814.791us 48 50 96.00
security_escalation 258 260 99.23
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_prog_failure 4.200s 127.320us 50 50 100.00
lc_ctrl_errors 12.980s 814.791us 48 50 96.00
lc_ctrl_security_escalation 10.820s 2744.101us 50 50 100.00
lc_ctrl_jtag_state_failure 59.940s 6647.857us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.890s 6240.982us 20 20 100.00
lc_ctrl_jtag_errors 53.430s 5761.544us 20 20 100.00
jtag_access 210 210 100.00
lc_ctrl_jtag_smoke 15.280s 800.706us 20 20 100.00
lc_ctrl_jtag_state_post_trans 17.510s 2589.022us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.890s 6240.982us 20 20 100.00
lc_ctrl_jtag_errors 53.430s 5761.544us 20 20 100.00
lc_ctrl_jtag_access 18.040s 3961.276us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 23.570s 1168.313us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.240s 1193.954us 10 10 100.00
lc_ctrl_jtag_csr_rw 1.810s 57.837us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 40.200s 5126.109us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.510s 842.308us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.620s 49.593us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.170s 225.906us 10 10 100.00
lc_ctrl_jtag_alert_test 2.000s 316.264us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 17.340s 4046.792us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.700s 141.474us 50 50 100.00
stress_all 46 50 92.00
lc_ctrl_stress_all 532.780s 96016.442us 46 50 92.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.510s 107.426us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 4.270s 142.845us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 4.270s 142.845us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.250s 27.190us 5 5 100.00
lc_ctrl_csr_rw 1.290s 16.704us 20 20 100.00
lc_ctrl_csr_aliasing 1.340s 16.314us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.070s 94.145us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.250s 27.190us 5 5 100.00
lc_ctrl_csr_rw 1.290s 16.704us 20 20 100.00
lc_ctrl_csr_aliasing 1.340s 16.314us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.070s 94.145us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
lc_ctrl_tl_intg_err 3.690s 201.562us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 3.690s 201.562us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 15.980s 693.239us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 12.870s 350.373us 50 50 100.00
lc_ctrl_sec_cm 9.500s 1281.562us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.820s 2744.101us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 8.360s 492.631us 50 50 100.00
lc_ctrl_jtag_state_post_trans 17.510s 2589.022us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.780s 2512.107us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 11.780s 2512.107us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 12.920s 3786.635us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 10.510s 1876.956us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 10.510s 1876.956us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 50 40.00
lc_ctrl_stress_all_with_rand_reset 112.280s 7858.877us 20 50 40.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 27 test runs
lc_ctrl_stress_all_with_rand_reset 10525351937389422171769131857021799696200562798175783460203314684832699819659 372
UVM_INFO @ 680782746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 94949885366609004111425961110965806897233006825709525640333939178943532590152 220
UVM_INFO @ 1019125309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91718286344997843290682352247145323441427125316053514831699171650371854822211 208
UVM_INFO @ 192257723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 15164610195301258477430299957536787046797530049679182542218404091744881387252 851
UVM_INFO @ 1934948618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43748768186563888628162574331310285603605107046974675228285214971065611107716 202
UVM_INFO @ 545934026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 24775264692643123798763576244044415432697893347182310400568645314493759743653 4968
UVM_INFO @ 8040248334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33796114043267472731614193430567871767632635197103462804710568756717161495278 150
UVM_INFO @ 115223165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 42391023336622578566510112941381823469539446250060969811758285923422106035192 4851
UVM_INFO @ 3024481718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57628516343145755399134012977916241983029975228416071913424498029789869961303 4085
UVM_INFO @ 4185154711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 57216614284267042012666058407682761851129326253449963555657848047225467315301 4706
UVM_INFO @ 4746404561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 16532511096966979721239891167113233717405047090658003660501396585741761121147 1108
UVM_INFO @ 6517781234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 84228003946792625217658143670163820641789059474974451835612546759640072466508 354
UVM_INFO @ 4546185913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 26448905826436543168942892566723718194235742183445116296278030250481371327952 150
UVM_INFO @ 107980265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 22496136673423358580069558604692412022665207436111884343958396929071892345456 203
UVM_INFO @ 336990090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 10561339690277622627604678924595761548554233529830381092846766341952453435616 169
UVM_INFO @ 7363473919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 103745120438577731176365827371025874680497377596324425707283581394972337891292 2462
UVM_INFO @ 2124197301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1125062553236664386980494180541116923393488669032637109400374150206862575555 5707
UVM_INFO @ 7858877497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37356471099418226042776135014600779838044196989517765826794540505188791001942 3811
UVM_INFO @ 5203134933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 80592637893688564037334597075882021673645820824613193090996496887836996774879 8058
UVM_INFO @ 18780862995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 106948632078452868011669148812056822687508506981950733998808654695739008375861 721
UVM_INFO @ 15408734827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91711326835125005066635477804613320745166603942289991933826794977739497921826 1351
UVM_INFO @ 4596755701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 97955459028537475424535834978041487164137695451551525732117787036795194026562 151
UVM_INFO @ 1176079750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 33798146130625915815596872954313857144016713163770774236026276134422426678515 151
UVM_INFO @ 224137229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86247019111752616521243294776085559188624287185459347906320803886429531005315 924
UVM_INFO @ 4042825365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 77770839597029977255121492180698545209912892986969582614160721496228317207152 8135
UVM_INFO @ 11340457867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87708947915641128408399590693605439098852300961292254972442320561703597864620 253
UVM_INFO @ 3291585412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 91254863405735803377479030296912733733665452258075239278561534381152139105783 4682
UVM_INFO @ 1922894896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 6 test runs
lc_ctrl_stress_all 1602181743863608014693864132444221647721798962790342456562779755732142883883 3557
UVM_INFO @ 22057060178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 33632078376080717813846687396979178711176890909884714247750536989710030381847 2541
UVM_INFO @ 536585339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 23003434147273347056171678335207330162129170690803566022047820228502085190597 2833
UVM_INFO @ 1920120828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 41149053739463541580121103387047227484969401065551862099176438164683868997586 982
UVM_INFO @ 120480389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 60236670076627969016804819789754697490854986386037811999308006433267159756377 1084
UVM_INFO @ 127454640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 19540104345511185214066044252894170980622504449513549098429748009254869185564 2620
UVM_INFO @ 5179836030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 2 test runs
lc_ctrl_stress_all_with_rand_reset 43897210783763965069895174896792535267530797078508243758327274580812490529681 8050
UVM_INFO @ 1756621376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 18077091767294499915225404238870348352652738717043042896060691482306341921054 3108
UVM_INFO @ 3925255970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 112337041139685290720294910136734291306319437678232446540017130967281417988899 3779
UVM_INFO @ 320860333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---