Simulation Results: otbn

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.58 %
  • code
  • 95.67 %
  • assert
  • 97.06 %
  • func
  • 100.00 %
  • block
  • 99.46 %
  • line
  • 99.60 %
  • branch
  • 93.06 %
  • toggle
  • 90.01 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
98.55%
V2S
96.17%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 38.000s 73.405us 1 1 100.00
single_binary 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 38.000s 40.829us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 39.000s 30.593us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 39.000s 277.772us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 38.000s 14.472us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 40.000s 36.144us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 39.000s 30.593us 20 20 100.00
otbn_csr_aliasing 38.000s 14.472us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 138.000s 27205.213us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 58.000s 185.642us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 63.000s 127.189us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 78.000s 762.126us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 549.000s 2103.000us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 181.000s 6447.068us 10 10 100.00
lc_escalation 56 60 93.33
otbn_escalate 68.000s 299.112us 56 60 93.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 37.000s 19.631us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 51.000s 75.404us 10 10 100.00
alert_test 50 50 100.00
otbn_alert_test 38.000s 59.584us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 37.000s 30.583us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 42.000s 450.307us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 42.000s 450.307us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 38.000s 40.829us 5 5 100.00
otbn_csr_rw 39.000s 30.593us 20 20 100.00
otbn_csr_aliasing 38.000s 14.472us 5 5 100.00
otbn_same_csr_outstanding 39.000s 18.105us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 38.000s 40.829us 5 5 100.00
otbn_csr_rw 39.000s 30.593us 20 20 100.00
otbn_csr_aliasing 38.000s 14.472us 5 5 100.00
otbn_same_csr_outstanding 39.000s 18.105us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 23 25 92.00
otbn_imem_err 38.000s 25.900us 9 10 90.00
otbn_dmem_err 38.000s 16.173us 14 15 93.33
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 36.000s 21.741us 5 5 100.00
otbn_controller_ispr_rdata_err 36.000s 62.701us 5 5 100.00
otbn_mac_bignum_acc_err 35.000s 188.991us 5 5 100.00
otbn_urnd_err 33.000s 110.298us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 32.000s 69.510us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 38.000s 34.379us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 35.000s 24.874us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
otbn_tl_intg_err 69.000s 207.099us 20 20 100.00
passthru_mem_tl_intg_err 19 20 95.00
otbn_passthru_mem_tl_intg_err 68.000s 261.682us 19 20 95.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 38.000s 73.405us 1 1 100.00
sec_cm_data_mem_integrity 14 15 93.33
otbn_dmem_err 38.000s 16.173us 14 15 93.33
sec_cm_instruction_mem_integrity 9 10 90.00
otbn_imem_err 38.000s 25.900us 9 10 90.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 69.000s 207.099us 20 20 100.00
sec_cm_controller_fsm_global_esc 56 60 93.33
otbn_escalate 68.000s 299.112us 56 60 93.33
sec_cm_controller_fsm_local_esc 38 40 95.00
otbn_imem_err 38.000s 25.900us 9 10 90.00
otbn_dmem_err 38.000s 16.173us 14 15 93.33
otbn_zero_state_err_urnd 37.000s 19.631us 5 5 100.00
otbn_illegal_mem_acc 32.000s 69.510us 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 38.000s 25.900us 9 10 90.00
otbn_dmem_err 38.000s 16.173us 14 15 93.33
otbn_zero_state_err_urnd 37.000s 19.631us 5 5 100.00
otbn_illegal_mem_acc 32.000s 69.510us 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 56 60 93.33
otbn_escalate 68.000s 299.112us 56 60 93.33
sec_cm_start_stop_ctrl_fsm_local_esc 38 40 95.00
otbn_imem_err 38.000s 25.900us 9 10 90.00
otbn_dmem_err 38.000s 16.173us 14 15 93.33
otbn_zero_state_err_urnd 37.000s 19.631us 5 5 100.00
otbn_illegal_mem_acc 32.000s 69.510us 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 34.000s 44.849us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 36.000s 68.547us 5 5 100.00
sec_cm_rnd_bus_consistency 4 5 80.00
otbn_rnd_sec_cm 87.000s 300.780us 4 5 80.00
sec_cm_rnd_rng_digest 4 5 80.00
otbn_rnd_sec_cm 87.000s 300.780us 4 5 80.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 38.000s 17.713us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 6 10 60.00
otbn_rf_bignum_intg_err 39.000s 216.833us 6 10 60.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 36.000s 14.632us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 36.000s 14.632us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 35.000s 26.646us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 549.000s 2103.000us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 46.000s 74.798us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 38.000s 133.797us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 265.000s 1329.622us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 510.000s 4783.700us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 37.000s 33.023us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 6 test runs
otbn_stress_all_with_rand_reset 36267702911527007793159974812542884303934494494968480590136170280106171847858 190
UVM_INFO @ 652104685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 106559154881939656507721206267906886940871773488725204586954646098567717783458 333
UVM_INFO @ 4783699597 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 97973131312289608647608368794138430743729006428580024778125851684211189972561 167
UVM_INFO @ 538755893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 95067771522886710713324744920927992757008797091777538915195849250605826715046 246
UVM_INFO @ 472958510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 110729119914635884442661959904154958632876453197149201556879158845741279223418 183
UVM_INFO @ 1062500535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 77254101502133263494838241795627178363283027935671984042152157144392035263753 237
UVM_INFO @ 288822339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 4 test runs
otbn_rf_bignum_intg_err 90196710647870778501464741947739966750472844915261919487360319791704014479973 118
UVM_INFO @ 154584057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 69584469694234588200664843521426134508028789788276785982095745039381107580125 114
UVM_INFO @ 187041796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 43399571056558092374861409813802776159540264451880987850294883559259455915459 114
UVM_INFO @ 38689111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 83506610428687076166685290926183567554883691677826141154489396786223739561717 117
UVM_INFO @ 91717365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 3 test runs
otbn_stack_addr_integ_chk 109999018656736936527528626059346691276830394974596076790666754388640902325726 120
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 397582744 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 397582744 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 397582744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 20220397771869908649042866748786377862568628033430052042543308305295985044324 113
UVM_ERROR @ 30760229 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 30760229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 66361744869786531039281646263819598163873982758610098757876373151185993614288 120
UVM_ERROR @ 31483598 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 31483598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_imem_err_vseq] expect alert:fatal to fire 1 test run
otbn_imem_err 105934499621296988268806091045317176338174349673954302004743008610640600365042 164
UVM_INFO @ 25899802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_rnd_sec_cm 100515827478817622937263460970658314724396668760597184068820639491816873961712 120
UVM_INFO @ 229436256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 31121105735808943268227235697942400024570978512911819927348249841921206123212 108
UVM_INFO @ 1442686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_dmem_err_vseq] expect alert:fatal to fire 1 test run
otbn_dmem_err 108260840676554403093862797184468295085035268130947942255262144955748452648604 115
UVM_INFO @ 30373206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 66147360946388047629231229176763643863979229238241819136735316769288547416048 106
UVM_INFO @ 148741572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_escalate 114820869193034100552311364856975547454641725052638485506422159762857079838438 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1