Simulation Results: otp_ctrl

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.29 %
  • code
  • 86.37 %
  • assert
  • 94.75 %
  • func
  • 92.74 %
  • line
  • 90.45 %
  • branch
  • 86.94 %
  • cond
  • 94.10 %
  • toggle
  • 95.76 %
  • FSM
  • 64.58 %
Validation stages
V1
93.97%
V2
95.84%
V2S
94.32%
V3
26.73%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.780s 55.886us 1 1 100.00
smoke 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
csr_hw_reset 5 5 100.00
otp_ctrl_csr_hw_reset 3.450s 1069.514us 5 5 100.00
csr_rw 20 20 100.00
otp_ctrl_csr_rw 2.340s 662.289us 20 20 100.00
csr_bit_bash 5 5 100.00
otp_ctrl_csr_bit_bash 8.200s 1785.241us 5 5 100.00
csr_aliasing 5 5 100.00
otp_ctrl_csr_aliasing 4.770s 1200.175us 5 5 100.00
csr_mem_rw_with_rand_reset 13 20 65.00
otp_ctrl_csr_mem_rw_with_rand_reset 3.610s 1685.558us 13 20 65.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otp_ctrl_csr_rw 2.340s 662.289us 20 20 100.00
otp_ctrl_csr_aliasing 4.770s 1200.175us 5 5 100.00
mem_walk 5 5 100.00
otp_ctrl_mem_walk 1.830s 564.072us 5 5 100.00
mem_partial_access 5 5 100.00
otp_ctrl_mem_partial_access 1.550s 148.724us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.530s 643.777us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 7.200s 2288.992us 300 300 100.00
partition_check 42 60 70.00
otp_ctrl_background_chks 21.800s 12852.206us 10 10 100.00
otp_ctrl_check_fail 92.530s 15632.728us 32 50 64.00
regwen_during_otp_init 50 50 100.00
otp_ctrl_regwen 11.330s 3864.028us 50 50 100.00
partition_lock 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
interface_key_check 50 50 100.00
otp_ctrl_parallel_key_req 38.580s 2310.051us 50 50 100.00
lc_interactions 250 250 100.00
otp_ctrl_parallel_lc_req 20.480s 1513.510us 50 50 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_dai_errors 48 50 96.00
otp_ctrl_dai_errs 38.110s 23823.093us 48 50 96.00
otp_macro_errors 25 50 50.00
otp_ctrl_macro_errs 54.870s 8812.561us 25 50 50.00
test_access 50 50 100.00
otp_ctrl_test_access 33.180s 5080.523us 50 50 100.00
stress_all 48 50 96.00
otp_ctrl_stress_all 657.410s 84532.365us 48 50 96.00
intr_test 50 50 100.00
otp_ctrl_intr_test 2.030s 107.156us 50 50 100.00
alert_test 50 50 100.00
otp_ctrl_alert_test 3.920s 430.013us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otp_ctrl_tl_errors 5.980s 235.288us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otp_ctrl_tl_errors 5.980s 235.288us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otp_ctrl_csr_hw_reset 3.450s 1069.514us 5 5 100.00
otp_ctrl_csr_rw 2.340s 662.289us 20 20 100.00
otp_ctrl_csr_aliasing 4.770s 1200.175us 5 5 100.00
otp_ctrl_same_csr_outstanding 4.130s 1795.130us 20 20 100.00
tl_d_partial_access 50 50 100.00
otp_ctrl_csr_hw_reset 3.450s 1069.514us 5 5 100.00
otp_ctrl_csr_rw 2.340s 662.289us 20 20 100.00
otp_ctrl_csr_aliasing 4.770s 1200.175us 5 5 100.00
otp_ctrl_same_csr_outstanding 4.130s 1795.130us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
tl_intg_err 24 25 96.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
otp_ctrl_tl_intg_err 55.530s 10934.016us 19 20 95.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_bus_integrity 19 20 95.00
otp_ctrl_tl_intg_err 55.530s 10934.016us 19 20 95.00
sec_cm_secret_mem_scramble 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
sec_cm_part_mem_digest 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_dai_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_lci_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
sec_cm_kdi_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
sec_cm_part_fsm_local_esc 225 250 90.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_ctrl_macro_errs 54.870s 8812.561us 25 50 50.00
sec_cm_scrmbl_fsm_local_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
sec_cm_timer_fsm_local_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_dai_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_lci_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
sec_cm_kdi_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
sec_cm_part_fsm_global_esc 225 250 90.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_ctrl_macro_errs 54.870s 8812.561us 25 50 50.00
sec_cm_scrmbl_fsm_global_esc 200 200 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
sec_cm_timer_fsm_global_esc 205 205 100.00
otp_ctrl_parallel_lc_esc 22.910s 17613.102us 200 200 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 7.200s 2288.992us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 32 50 64.00
otp_ctrl_check_fail 92.530s 15632.728us 32 50 64.00
sec_cm_part_mem_regren 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
sec_cm_part_mem_sw_unreadable 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
sec_cm_part_mem_sw_unwritable 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
sec_cm_lc_part_mem_sw_noaccess 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
sec_cm_access_ctrl_mubi 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
otp_ctrl_dai_lock 41.300s 20180.479us 50 50 100.00
sec_cm_test_bus_lc_gated 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 269.440s 155855.364us 5 5 100.00
sec_cm_direct_access_config_regwen 50 50 100.00
otp_ctrl_regwen 11.330s 3864.028us 50 50 100.00
sec_cm_check_trigger_config_regwen 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
sec_cm_check_config_regwen 50 50 100.00
otp_ctrl_smoke 11.800s 4329.020us 50 50 100.00
sec_cm_macro_mem_integrity 25 50 50.00
otp_ctrl_macro_errs 54.870s 8812.561us 25 50 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.070s 5975.134us 1 1 100.00
stress_all_with_rand_reset 26 100 26.00
otp_ctrl_stress_all_with_rand_reset 219.220s 77072.288us 26 100 26.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 60 test runs
otp_ctrl_check_fail 49535040563627259995866657226727195350842317719411051590198434602691299628295 10379
UVM_INFO @ 1159788532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 24364233576289370532704596477224510190498195123062769294095296056537824343435 14852
UVM_INFO @ 828783886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45693374638860432096712469841570214718358185012610440796644073688385654165152 417
UVM_INFO @ 252118435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 14416919728860215697478982818153503960673540293821720828327910889212709190760 3615
UVM_INFO @ 313724580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 26686735657505613701241907915803287025194172381222622153382563925493546467249 4607
UVM_INFO @ 1281537638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 5903067197693801524033728018569356081586796739005163505182844406695373624546 2383
UVM_INFO @ 138408276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 878090568159633359607529336021267973648781253888815621349489386591115833430 1224
UVM_INFO @ 744435541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 88988301081918140156013528253372697619121013851185665312160628599166991735258 171
UVM_INFO @ 50714294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 32658104201010142044531903572831034115693431611162013994089625325934854673583 155
UVM_INFO @ 174588373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 12475165183567649654845276194907912165565730538821994880027750019662029296976 13881
UVM_INFO @ 1273677865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 67838618978685257411891861297801216113375867597648265391161836411708663932279 607
UVM_INFO @ 334603399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10383834694972059233931751328378611291765974725150260889548873180668518320820 157
UVM_INFO @ 53000508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 2329815316829368336319207635861040354596947987981060710199639891981900682449 313
UVM_INFO @ 131134716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 50877378820155001861806967585821349325883457393142227680979794350506272812646 3405
UVM_INFO @ 1093610704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 2894559655264372346693724427343603919578081088346894669483798579951196520959 3000
UVM_INFO @ 1344687359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 103581700258349252192296148286155640923464952056979431878498033238582105738399 10049
UVM_INFO @ 1242175950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 96414217902267276070092456217654463583128009262792812421602414705932501085865 8829
UVM_INFO @ 468981206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 45979160752346450730774395975087943868250129394400868159793997866495031270282 15963
UVM_INFO @ 1695570579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 16869547627688085236874259443235785576742046912911616854854860226094637857871 15420
UVM_INFO @ 813174021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 45321352408495508424554958148874436224166315518971196664836676857081016597027 10993
UVM_INFO @ 917523643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 11459639163885267163824696347022420700754025542998392898465366987149429504932 109
UVM_INFO @ 61510903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 24881219573602339373390898666570050483773367991576726043168013901627050878397 3190
UVM_INFO @ 2155381349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 28658262730361045022291268867762518360519009173901082177618768475021647980077 7504
UVM_INFO @ 935278081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 24887775171119201715929647142004473960489596325229507921997649705596249107357 9001
UVM_INFO @ 634620735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 64408494612696814599465671680919277033360029241452713568309431171803167215382 9622
UVM_INFO @ 847066435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 78400971545840537230698211027736284102798916541239979084091482872529854997489 21285
UVM_INFO @ 5489586589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 53581108737097758823304959851506058082085318468615469349887628575113119490064 419
UVM_INFO @ 107619924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 41952331809639626567364277796676763255805980254976625770034112707723503928700 775
UVM_INFO @ 115438169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 84268801524760925309363009712137681438226844788801141812009150682134020949932 737
UVM_INFO @ 232435374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 96820672065958571332437289678790162700954047549534787372591669852450312923280 2726
UVM_INFO @ 1202361371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 104034729475093890564033131981332474485163220316775571580826911875538835397573 1501
UVM_INFO @ 2007838704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 82505624870033588468988621422998696583837554090256874775897486354651853992253 12936
UVM_INFO @ 1760747573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 48267692841627882180174731059461885027604962595070224972665698620162872015593 1577
UVM_INFO @ 3037131490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 20006466953462051391241754679487057046860308063790061787007377744112822997659 7982
UVM_INFO @ 1361981791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 61763372568740492314411924684928858247942162267675140876112551559589627577394 3492
UVM_INFO @ 265863110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 86341752052104262334815806024734425655678292994017923437920043197696448144480 2261
UVM_INFO @ 125266624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 11277820623021737863242629242959574967529743516026980432087478003163709249386 2456
UVM_INFO @ 182684243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 43692214365314914950934569995298652345194176473219832515032875475770425966480 4114
UVM_INFO @ 316308705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 97046766507678220197256358655061245014233521472257844379139581342552975679850 277
UVM_INFO @ 39316394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 95977123416740058221066968104307864198575950288073578067970754782173003571037 4731
UVM_INFO @ 1123975087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 64654341327232765763053952158856535880352587588932135182345402724893519674292 15123
UVM_INFO @ 1935300799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26540551433918119839634225279032082320749857086078218901435538875481565836891 15468
UVM_INFO @ 492296517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23169127665341849919982080728770595520754636667759531511436771573232427730792 1213
UVM_INFO @ 983957049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 67545781713906483865192251775908830605479395391570569506620743489273592506066 695
UVM_INFO @ 392209318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 48753998149125262555997621741846034849920189993557047463415236211158657554827 16936
UVM_INFO @ 770612997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 94112362260185669543479674870050595682210908716067709252038163947652601771111 8573
UVM_INFO @ 8308871012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 102587772272685794598834905642216394125869619036003078867375510009096091874910 4681
UVM_INFO @ 822246961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 21696761389878028026136145941610400981186421980785592038023930436300227097158 6794
UVM_INFO @ 707295210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 9297961838473258347539601412956120265467377247290653643043894459824577900774 21024
UVM_INFO @ 25212725241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26565609925061558605959087621651013652652746165698561734041584782692201911638 8652
UVM_INFO @ 2119441819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 111732022545876675060636572060407200906481707285449365411108928166698410004632 106527
UVM_INFO @ 10788901463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 72827860894280080353082108614258549508094526546410553788228760925610685790949 4805
UVM_INFO @ 5043420448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 56876805020096930075113993246278767531367391635161097564770049144529869377549 7532
UVM_INFO @ 2853715089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100019050207785163229434134972196418597999382993009638772247256076206214113191 121
UVM_INFO @ 514354161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 66213968354562750018453648714596606713900347635476304391170575472763908640019 7772
UVM_INFO @ 16159520824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 16789776865387183438257373406060340448965741927335704724492896861651445345691 129
UVM_INFO @ 306392211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23056775238221459447944635919201234744409731569800766399987011500321460504763 28614
UVM_INFO @ 5426555692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55543752249264699144329267914651089264119235216778086371265025880792488025814 37895
UVM_INFO @ 3011691199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25205544517346962111388210663812141045226988052298024248591957818240877244907 1542
UVM_INFO @ 1547680649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53504953063121041819462998107563754206169211836398587197784341759268665994080 4936
UVM_INFO @ 1545569530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 42 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 98647532702418453098074238606414861719682673801831737931847335093982647920252 92
UVM_INFO @ 63955189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44218556371866173845694327833792347170951827003481701830473679958555115671424 19771
UVM_INFO @ 2059866618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 39778083547094505518315700048697396888972293443879048598263801249824058606527 92
UVM_INFO @ 26722893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 49451694667021903522593325097691825646996666858684103874244940166873605885619 8220
UVM_INFO @ 971229495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52493440480031427662970889618076200568210171126570992839028107295612960359538 12294
UVM_INFO @ 1362612573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23133754411002817162735943609798099489877418560543832857933045341643277740038 23898
UVM_INFO @ 10432018824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 83292720626308368885057003860913616756828975049809074723410293095073040663510 92
UVM_INFO @ 26474090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50195586051164271192976079625891999010114438857498847773057192767718987236637 92
UVM_INFO @ 60918378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68692853311077930160334807240699141682311304930327999956753250751694852040470 12227
UVM_INFO @ 4704964649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44240476339050722244774620113196749708550060231814628726006569879320520183730 74987
UVM_INFO @ 77072287672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 68445665882885890016425268231607854932571305109454445404520198291157359995508 34964
UVM_INFO @ 2943258815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102017801363672596977155112839280555434034509109176468334030742210004875650019 192
UVM_INFO @ 6704034774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 60670282184373574153738666056255108162544763799942551430927468118497803492465 1517
UVM_INFO @ 1673827871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 61440983738272253426585769961349841949467836530736961518251924419011654065064 176
UVM_INFO @ 124450905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81873131660670854156297041617105055776104264574956475428990403457523582190376 92
UVM_INFO @ 29782221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13899760350413619916685198280357864005080512079043769065653621118799091877254 31316
UVM_INFO @ 4293080718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35411017544201535468395607639291909633199945592037647685829278597605650398426 17151
UVM_INFO @ 3760807113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 29977568393858515087457153929577391532413089022799594464504554891975439409784 1396
UVM_INFO @ 1145842564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 38192935189306817632584648778607260543724417927133753240173379623343922544285 16335
UVM_INFO @ 1209940169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 22901452486706426602250593121808085709538955176677378196229709859299983281123 92
UVM_INFO @ 40853595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82704436371360398745733243675644670725777946563226397403435687853332359455184 13836
UVM_INFO @ 926027987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 75427758355627457861785770607064975092693387419299699690915246181662175611981 1092
UVM_INFO @ 5877888426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13104600981379516297954875494471139983015259802160954540834132099966646082661 7554
UVM_INFO @ 20542735092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83304583391062215503939121527908169394534348529903636883195698816593828690608 1559
UVM_INFO @ 10031750522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35169984512729333375789906068990499669114208416995166076197184593017934524564 9626
UVM_INFO @ 826153202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54103093344162223427294296264202647317062085975680756648894848603302862556703 9781
UVM_INFO @ 4448448930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50759330667180139711456514024435442102951537146057458426245361271600922722983 16375
UVM_INFO @ 2217948676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52944426257870823024005586151616936617755643101378805778511112060641959887380 10293
UVM_INFO @ 16419057976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 6552238063710138618666793650561490536333600723742026776165397019667641082254 324
UVM_INFO @ 330202208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 13320136621802667634181072837212558136131631022295620023787271256320017949922 1132
UVM_INFO @ 426673994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 78303353167536200492869290097728639462277952769074791570763520382313772420880 26998
UVM_INFO @ 1087846007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 47763661934694666314553180242499309380947963671841625165466913922101337702735 6844
UVM_INFO @ 1262358333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5392380789488175007731464295046126359933693445726761303861805440268262577786 27654
UVM_INFO @ 44878242354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79153883811793833441485523228917915828805122399879984623098192008334330869871 4755
UVM_INFO @ 24513124276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 44317822708552539570638679155695474074841650458122786261415696129637501455703 25128
UVM_INFO @ 18212824886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 12703569809011865331732285214830951224705272759737218175331485540435663351066 5832
UVM_INFO @ 5287678547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 24047684576203760552345649816633108807670185273643980777215600023297313280797 93
UVM_INFO @ 69210811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 46799494093214827014095211847920864213430033766822340985181567981643055976388 93
UVM_INFO @ 25958269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91543070664128504230917373610234049057606377148203914289276890103659549855863 92
UVM_INFO @ 26491172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51729314207950837893652106251004132553453039161689735109430996876934702618470 406
UVM_INFO @ 402494507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 100661488387611534867201410738871020838415420535118901306110788800764070503982 92
UVM_INFO @ 57927109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7909874613276479615070754513866216890672710211150011365959134497342655111447 92
UVM_INFO @ 104403935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 11 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 641314289628105225627599916312158650401217204323875573420086970182366285638 92
UVM_INFO @ 54061781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 72177993136714984594318056675007787586300356364418686143194093290463825807188 98
UVM_INFO @ 977895201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 93636893026363590764989346876705482736029801644839760490511346852889541658428 92
UVM_INFO @ 52510710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 60401643778702575511903467860425418289914428222031807883557044657554513976219 92
UVM_INFO @ 431105129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 51678327997470124827117248422378077456207820653632232596967643468835681604104 9147
UVM_INFO @ 1647167344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 111939264715123860256486131840169930593911658988574975817643047377444323819006 844
UVM_INFO @ 241576742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 76116041650992157958460440729310517552717624841842163073103673527868168281530 92
UVM_INFO @ 26527468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 83650575990698515697839249681610935370501717183044252487814573800418448966395 92
UVM_INFO @ 36048216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52335526301479323240852737602112895693723240363812597037619301388736357384360 92
UVM_INFO @ 31499770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 35721392832326548355985446413510726359305118641657550916845866293217962200281 4021
UVM_INFO @ 1036135113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70548486980313260609525168534237054968302620984926477213394855317091395374058 8038
UVM_INFO @ 8378454678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 8 test runs
otp_ctrl_stress_all_with_rand_reset 68058176652384808204657969554591782786282645526266167530740791944840678514706 292
UVM_INFO @ 13283190924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 10656209333504153267427675351966276578303769251200955352035408351224534028984 127
UVM_INFO @ 109965610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1810174373834177266002190791275513486981240022533019796755807338728199069180 6679
UVM_INFO @ 448768656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62928957228730943958597367690517510521626713726917875881536200859618777773031 6006
UVM_INFO @ 14122931373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18619261369603719437622896269425868336498092878190645143378871359527672165532 13975
UVM_INFO @ 15587267602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88872750990261635165341819499738738442366934199334152722715763551111543670234 1471
UVM_INFO @ 484991109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 52445336102841194264227936771706748220647158991584002778955589105301220618255 4225
UVM_INFO @ 625044244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79316763692331555160515007559646989001156858209540162478048083767560608409584 14519
UVM_INFO @ 5847035524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 29326038751253791946110060540614408198545031497856249123642059366521824732579 4290
UVM_INFO @ 3446859277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed 1 test run
otp_ctrl_stress_all_with_rand_reset 78504435851740756643661083855732930557742976431395726562105574149226352847215 7658
UVM_INFO @ 17882085887 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 17953500180 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 17953638112 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_INFO @ 17953845010 ps: (otp_ctrl_scoreboard.sv:586) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state 1
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *f* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 39022703604969515223312286740403416975075909656060876048884366004544467308591 38917
UVM_INFO @ 9305290658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_tl_intg_err 7334330199693201425242818338345913003079107718404941901815053915466800565495 185
UVM_INFO @ 10934015740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otp_ctrl_stress_all_with_rand_reset 109355002179417921236077025615938332671152629577677787627935357716408165294791 5990
UVM_INFO @ 13996189468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(cio_test_en_o == *)' 1 test run
otp_ctrl_stress_all_with_rand_reset 86330052805828355265816741837655988667078380006300728708682630234368273824258 661
UVM_ERROR @ 20475495013 ps: (otp_ctrl_if.sv:297) [ASSERT FAILED] CioTestEnOWithDftOff_A
UVM_INFO @ 20475495013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen 1 test run
otp_ctrl_stress_all_with_rand_reset 18477237587019061479747323116531784607563351954759835245119905821123869557922 11606
UVM_INFO @ 7028011432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=263) 1 test run
otp_ctrl_stress_all_with_rand_reset 95948822283512347744911289786496722386934293713033472586850389886521096666149 17959
UVM_INFO @ 44596788092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---