| V1 |
|
100.00% |
| V2 |
|
87.03% |
| V2S |
|
100.00% |
| V3 |
|
2.00% |
| unmapped |
|
64.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 50 | 50 | 100.00 | |||
| pattgen_smoke | 5.000s | 143.285us | 50 | 50 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 15.199us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 12.100us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| pattgen_csr_bit_bash | 3.000s | 112.907us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| pattgen_csr_aliasing | 2.000s | 21.672us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| pattgen_csr_mem_rw_with_rand_reset | 2.000s | 20.757us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| pattgen_csr_rw | 2.000s | 12.100us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 21.672us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| perf | 32 | 50 | 64.00 | |||
| pattgen_perf | 3600.000s | 0.000us | 32 | 50 | 64.00 | |
| cnt_rollover | 50 | 50 | 100.00 | |||
| cnt_rollover | 75.000s | 6261.383us | 50 | 50 | 100.00 | |
| error | 50 | 50 | 100.00 | |||
| pattgen_error | 2.000s | 170.732us | 50 | 50 | 100.00 | |
| stress_all | 20 | 50 | 40.00 | |||
| pattgen_stress_all | 10801.000s | 0.000us | 20 | 50 | 40.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| pattgen_alert_test | 2.000s | 26.581us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| pattgen_intr_test | 2.000s | 14.393us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 116.803us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| pattgen_tl_errors | 3.000s | 116.803us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 15.199us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 2.000s | 12.100us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 21.672us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 20.666us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| pattgen_csr_hw_reset | 2.000s | 15.199us | 5 | 5 | 100.00 | |
| pattgen_csr_rw | 2.000s | 12.100us | 20 | 20 | 100.00 | |
| pattgen_csr_aliasing | 2.000s | 21.672us | 5 | 5 | 100.00 | |
| pattgen_same_csr_outstanding | 2.000s | 20.666us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 379.350us | 20 | 20 | 100.00 | |
| pattgen_sec_cm | 1.000s | 351.649us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| pattgen_tl_intg_err | 2.000s | 379.350us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 50 | 2.00 | |||
| pattgen_stress_all_with_rand_reset | 146.000s | 6253.377us | 1 | 50 | 2.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 32 | 50 | 64.00 | |||
| pattgen_inactive_level | 216.000s | 10022.526us | 32 | 50 | 64.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. | 46 test runs | |||
| pattgen_stress_all_with_rand_reset | 36990748683412703282664420231150903737276471411760530470122081916955758461908 | 150 |
UVM_ERROR @ 1067115381 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1067115381 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1067157049 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88283652530571689796383598801784234003524204476476482269547742057353490818784 | 127 |
UVM_ERROR @ 4479185596 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 4479185596 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 4479852260 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 106578279895671025663663844957511253568229503931768186365187362486643181490183 | 116 |
UVM_ERROR @ 274670715 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 274670715 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 274701018 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 63094523129682203040503267397396675087222454224904957380875633392231662794402 | 223 |
UVM_ERROR @ 1072012994 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1072012994 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 1072082994 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 47378640254246179043407155008921834637163085413000205718779078868376993761577 | 161 |
UVM_ERROR @ 3934328518 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3934328518 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 3934828518 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 75540506734566523427682294703999312162212934162933390435035100355820317161821 | 176 |
UVM_ERROR @ 533754797 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 533754797 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/10
UVM_INFO @ 533852837 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 39091842431751891076965605827494657570476473589954036314982525292962228801240 | 225 |
UVM_ERROR @ 9552460820 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9552460820 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 9552860820 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 106275956743288147976536472948439323047818673160284291900493228666232458505270 | 127 |
UVM_ERROR @ 2475989701 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2475989701 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 2476156369 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 100453995800093084602197917578712149564939856938760142114745709272725863088595 | 176 |
UVM_ERROR @ 951158012 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 951158012 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 951210642 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 101543406076677330867038052160863177086956364442776059277608123820707606113874 | 126 |
UVM_ERROR @ 1015691329 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1015691329 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1015775537 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 32265853239830140907372694063222229298336404762361805237692959584254633234223 | 204 |
UVM_ERROR @ 2465285121 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2465285121 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 2465392263 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 81560571400536541599471215872710280311267907231204695099149372709820640678321 | 418 |
UVM_ERROR @ 13292035228 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 13292035228 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 8/10
UVM_INFO @ 13292191478 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 2675890107081728749842431385150825144538570974784256836596466367209478896984 | 126 |
UVM_ERROR @ 3185604721 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3185604721 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 3185854723 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 36551177718424452894962942990724120651407223132208521636781406050720292177735 | 116 |
UVM_ERROR @ 562306943 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 562306943 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 562327777 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 108476782308049409777699590921872728513711024620074272937002075157528888712504 | 117 |
UVM_ERROR @ 631466071 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 631466071 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 631567081 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 50493175484442452862880694326122227581650810883078900422397846148128100260722 | 165 |
UVM_ERROR @ 1400490793 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1400490793 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1400510793 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 84342732302601263602613333680562637937575936325186335227982723508232341939107 | 116 |
UVM_ERROR @ 715333095 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 715333095 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 715393095 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 102154301718498891174436218656275999096518544510773616317095384385782040717464 | 172 |
UVM_ERROR @ 1058411312 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1058411312 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1058585224 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 96185590517792274700972510777563922072572252980303782606095671676493684370717 | 142 |
UVM_ERROR @ 459648334 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 459648334 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 459773335 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 34511113876022587740064897543538790447368074776673918763203758473001381250511 | 127 |
UVM_ERROR @ 864855296 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 864855296 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 864947132 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 38172896387426107859574105934793016276593172860082804902669780444863341086935 | 193 |
UVM_ERROR @ 150071154 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 150071154 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 150091562 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 115008300408053588535152516159051445695928153168127229380204674060166365351743 | 119 |
UVM_ERROR @ 613910969 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 613910969 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 613941581 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 24823053227736931812383619631502851423475813977669156584268067055580019896458 | 163 |
UVM_ERROR @ 12432635406 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 12432635406 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 12433835406 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 2475021479306440524216689017927472573461820376226711087488337933247797764565 | 145 |
UVM_ERROR @ 2619501974 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2619501974 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2619585308 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 76577747833925185747463597762446451760102371138390409297515337959024185594787 | 113 |
UVM_ERROR @ 431403722 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 431403722 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 431483722 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 14431906010053910400198711436243331965218112406242068683570839508484517556518 | 127 |
UVM_ERROR @ 1026029045 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1026029045 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1026131085 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 84177163680102913401385316318159860880206994995233142045189140934760877509986 | 117 |
UVM_ERROR @ 929146553 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 929146553 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 929246553 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 27198138958996246924523774716253858564393988980050488265728008944331253778146 | 189 |
UVM_ERROR @ 1008387979 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1008387979 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 3/5
UVM_INFO @ 1008466411 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 109785705762858308803276021829076900981842728789461033402215692118189317906833 | 331 |
UVM_ERROR @ 9789042986 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 9789042986 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 6/10
UVM_INFO @ 9789459656 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 76157978883835628695660030861004425882750630967860222098129996507096728760163 | 250 |
UVM_ERROR @ 7623578077 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 7623578077 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/5
UVM_INFO @ 7623665033 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 34413943771215240777624222994162367018470509298691377019705759429895634920158 | 157 |
UVM_ERROR @ 772302405 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 772302405 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 772373112 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 4430380241643789439744881609728659326658795341861615717262764942338287899233 | 130 |
UVM_ERROR @ 778062647 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 778062647 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 778164687 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 42228133373278468947283296553016986215904478503254007358570207370750086250497 | 114 |
UVM_ERROR @ 293650261 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 293650261 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 293691358 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 88625851503196271319487690113027982763906275510495546019719839655409288875439 | 123 |
UVM_ERROR @ 1131823098 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1131823098 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1131925138 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 19795048101922483919082349749933007219444556742345607605321550228238429313078 | 133 |
UVM_ERROR @ 1848592509 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1848592509 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1848643791 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 68374669212797447192791953636788452981843907078780899795425235364663417360383 | 175 |
UVM_ERROR @ 13922563291 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 13922563291 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 13923188291 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 51040214399867444763398412567064763133774974081836659921190410087473827116355 | 139 |
UVM_ERROR @ 555323007 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 555323007 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 555343209 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 43427032135200469678144291757554688506168566924465643235559091973448407572793 | 114 |
UVM_ERROR @ 1295079005 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1295079005 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 1295339873 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 38492603622294890709402339664478620961163327510760965248255900314701874474444 | 133 |
UVM_ERROR @ 2581287506 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 2581287506 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 2581498034 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 13854529413365859794774220843413844538743124208215582469025643889358630511885 | 116 |
UVM_ERROR @ 535294669 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 535294669 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 535398839 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 37278888075072778219557919938243567391833675711142791327549068591150689613896 | 117 |
UVM_ERROR @ 380564069 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 380564069 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/10
UVM_INFO @ 380635497 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 16668470371189300836718660791116661394444943020771846285991797393600698539105 | 113 |
UVM_ERROR @ 1790522054 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1790522054 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 1790772054 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 100690066276616891241625869443808044843087072866320499704491824998806596315964 | 118 |
UVM_ERROR @ 15941302163 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 15941302163 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 15942502163 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 75505981828447584909619079156386254166355926998939743737533158579421269399663 | 163 |
UVM_ERROR @ 3319469190 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3319469190 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 3319599624 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 24597333885649474062873184954626369905237855317531010360292377334683556104454 | 150 |
UVM_ERROR @ 1354198702 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1354198702 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1354518702 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| pattgen_stress_all_with_rand_reset | 93475336072327580680550579572589085009641308153119166720070910768766218006943 | 147 |
UVM_ERROR @ 484855659 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 484855659 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 484975659 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
|
|
| Job timed out after * minutes | 18 test runs | |||
| pattgen_perf | 57541142254147305176483190072049747337136980697134305020754153376753711688699 | None | ||
| pattgen_stress_all | 88935089283296717852221546776065318778366200158489026698163323825017091720170 | None | ||
| pattgen_perf | 42296200956689609885009566385061213315216526733275562647585071876457758398207 | None | ||
| pattgen_stress_all | 6178511601631686658016786923485646246893041450330835041241085806377051129709 | None | ||
| pattgen_stress_all | 51448429117589473210746784695445745384575750703406749216409307982716017921792 | None | ||
| pattgen_perf | 13184219210756431517819382108324339050637343214081940746443194685694733186364 | None | ||
| pattgen_stress_all | 14809330136690572998113118767194656362719227461358020995305642804095069958091 | None | ||
| pattgen_stress_all | 90066332463566515074559653435321904047093988787031378649437372939770573346864 | None | ||
| pattgen_perf | 77416939828725662238331037308255121235038966899689834571108104912250720823795 | None | ||
| pattgen_stress_all | 100509428795620032270681938165049928727540138866241814610607422486895641614642 | None | ||
| pattgen_stress_all | 33120884744240170978483763188954102123614193237025571555215204743659952369982 | None | ||
| pattgen_stress_all | 109363048150368544826409694432545837787252137751797875910173928573423253098611 | None | ||
| pattgen_stress_all | 115240194360515377328445488168623806082737097473345221193256074940755777354307 | None | ||
| pattgen_stress_all | 13162070362160758416276294592426558965381964136709130322774650659567648038193 | None | ||
| pattgen_stress_all | 50411901633588024876900449628220439285468560662330301906104112582400275578428 | None | ||
| pattgen_perf | 93585469285167436307494598648735554212925253684339976773200878821779396065394 | None | ||
| pattgen_perf | 94821560874618661662843503367108411207841604469148965653805942273158210059267 | None | ||
| pattgen_stress_all | 101314522378970755956647089124610551071163211005630787406892120871688046602009 | None | ||
| UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: | 17 test runs | |||
| pattgen_stress_all | 97109311477484504237289682310683385437697347304777072355190263606807779848704 | 132 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11400
|
|
| pattgen_stress_all | 29661037947646833447058624436798460904582605558962492701664227751819707016127 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11321
|
|
| pattgen_stress_all | 82553600821672373519178865712961693696768659769450664601687673139338574741569 | 160 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11458
|
|
| pattgen_stress_all | 73296141137326360442377901055684242718907178248719327900546169657909388706788 | 149 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11502
|
|
| pattgen_stress_all | 15972749162730356167980005565167429184436338753906399172523741666048040824791 | 130 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11338
|
|
| pattgen_stress_all | 14266914465224665837891117954499428994240795908284923284109263121195349271056 | 135 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11352
|
|
| pattgen_stress_all | 71113233423373064240459949914030371549130124515172658898904380600705650509710 | 141 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11315
|
|
| pattgen_stress_all | 73293058419701903262608665619089574759897105151644239589289193240330035831803 | 145 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11301
|
|
| pattgen_stress_all | 50408178513551338988838888148106891224679301581894735206023028312860657364924 | 151 |
----------------------------------------
Name Type Size Value
----------------------------------------
exp_item pattgen_item - @11388
|
|
| pattgen_stress_all | 95407552946116694483240316169684197853044256697067122378250095978995455693788 | 130 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11322
|
|
| pattgen_stress_all | 114804073343929636056028491958492075716194262583656298615074857465376918826232 | 153 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11412
|
|
| pattgen_stress_all | 93890632079391301572388065049620618820238282770850662028433495464727470126430 | 146 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11270
|
|
| pattgen_stress_all | 94810009976096600417001705941236106986729601165480659342581796022521158190749 | 125 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11309
|
|
| pattgen_stress_all | 89781926802328529970797237047886460453115383905592976937937405373412657230491 | 140 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11365
|
|
| pattgen_stress_all | 69055572388769381885449471064678389766501777169485429827018140903289470146968 | 160 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11320
|
|
| pattgen_stress_all | 43770387472481197336042381828715030702102354872855378269905719706434900218134 | 140 |
--------------------------------------
Name Type Size Value
--------------------------------------
exp_item pattgen_item - @11377
|
|
| pattgen_stress_all | 61077209180543610206975520518865680243091571881194965989728608659283688729668 | 139 |
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11306
|
|
| UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue | 13 test runs | |||
| pattgen_perf | 37491378599994044794585770086886527198850762669005457115768806772643154743523 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 36165090206624659283678506172518930293742844387965382204691725610113238774160 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 29549612571648934743153847091015300263294762043755888781756924672860636020054 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 69507432437156957116960117032539021073865019616825890257328022694254075814637 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 91043903588282762717358229913414096549164464202948168570969140248741539823466 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 85456065753646208324522732837173892745963820332132346260091199036592297227351 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_stress_all | 107348718743444516783714847123517942917008180858400035315978996933265689074302 | 125 |
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 106200861437264699778265192405967111218112339511849133226245678301584185861948 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 12711249793061871166629469077144694511099700219626119422358517007921068143355 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 51215206141055378531148276209537833339614228172532175310849869828340529536976 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 25640667852787590258140094046385385625300050568510368763468154279855686765080 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 93445643581342672686476907707844240171789437481426209653686293602450831523179 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_perf | 14069874921069079079368277298046172326270679352635400890122137464619656723671 | 99 |
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) | 3 test runs | |||
| pattgen_inactive_level | 113235913885386714847612183773954674427340298798363565452153374572844187090002 | 99 |
UVM_INFO @ 10026690365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 50811680313027592017601081660430856789539786864261031023338471235854213322122 | 99 |
UVM_INFO @ 10004244622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 112722443069440141331758162833041188497578677370081054780267323229330803691169 | 99 |
UVM_INFO @ 10046822492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] | 3 test runs | |||
| pattgen_stress_all_with_rand_reset | 60614002221690239947455514188537147445480070179145824376951791704473669729185 | 144 |
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| pattgen_stress_all_with_rand_reset | 77937597095983176234357311676888634084805678408505481785205520982210194443754 | 132 |
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| pattgen_stress_all_with_rand_reset | 63805300451947476654122290527041326138341717174578645674468454581882366132740 | 180 |
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) | 2 test runs | |||
| pattgen_inactive_level | 25853064660398694911898001132207266520211329778615890173137857152566039121248 | 99 |
UVM_INFO @ 10017073290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 50957738120771278385922583879688912486981627384443582001994301905779695397981 | 99 |
UVM_INFO @ 10006481590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) | 2 test runs | |||
| pattgen_inactive_level | 89158278862970435409578098772095907937764522164450949070636962646052304993340 | 99 |
UVM_INFO @ 10029205796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 54038618903101129247479560950439457162881089168850882055724928485727514252596 | 99 |
UVM_INFO @ 10007959955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) | 2 test runs | |||
| pattgen_inactive_level | 66396313861416517556955109389049101265348255269163594166201207065951751671007 | 99 |
UVM_INFO @ 10039978704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| pattgen_inactive_level | 106821297467896437422681474913199878075670111952737806412145416960618423782254 | 99 |
UVM_INFO @ 10044726814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) | 1 test run | |||
| pattgen_inactive_level | 2501329780906219484135133179150494446255888131127152491326150212213536695500 | 99 |
UVM_INFO @ 10187736273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) | 1 test run | |||
| pattgen_inactive_level | 98266037892140653070175221454608714217291953831967501549973880736876675700190 | 99 |
UVM_INFO @ 10018283940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) | 1 test run | |||
| pattgen_inactive_level | 28457451011464581467353972105156100705490293854654825383764000893252425433405 | 99 |
UVM_INFO @ 10039748291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) | 1 test run | |||
| pattgen_inactive_level | 64034553745202922826911770308974842007289007596211578525266803189577903232933 | 99 |
UVM_INFO @ 10044427104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) | 1 test run | |||
| pattgen_inactive_level | 57585250417280047483969223802226457666875419782405873539097566147974190297023 | 99 |
UVM_INFO @ 10008536638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) | 1 test run | |||
| pattgen_inactive_level | 9768845437710231440053081519485973992489896233422544928530048683671383305907 | 99 |
UVM_INFO @ 10011104536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) | 1 test run | |||
| pattgen_inactive_level | 93090591900788417650944158724351844088217330737641447627242191600336343785158 | 99 |
UVM_INFO @ 10012291410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) | 1 test run | |||
| pattgen_inactive_level | 61318135579435970587256865003170608292187819490126162594567025177355860834253 | 99 |
UVM_INFO @ 10022526296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) | 1 test run | |||
| pattgen_inactive_level | 108965258760480885906130661406525916436824352078600582134359231941136476692544 | 99 |
UVM_INFO @ 10172214069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|