Simulation Results: rom_ctrl/32kb

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.75%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.980s 329.922us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 8.140s 877.782us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 7.040s 169.832us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 6.610s 165.099us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 6.200s 287.523us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.670s 576.490us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 7.040s 169.832us 20 20 100.00
rom_ctrl_csr_aliasing 6.200s 287.523us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 5.700s 282.918us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 5.080s 519.278us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 5.840s 573.986us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 26.230s 428.519us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 8.580s 545.402us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 8.720s 550.764us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 10.600s 185.963us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 10.600s 185.963us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.140s 877.782us 5 5 100.00
rom_ctrl_csr_rw 7.040s 169.832us 20 20 100.00
rom_ctrl_csr_aliasing 6.200s 287.523us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.470s 545.632us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 8.140s 877.782us 5 5 100.00
rom_ctrl_csr_rw 7.040s 169.832us 20 20 100.00
rom_ctrl_csr_aliasing 6.200s 287.523us 5 5 100.00
rom_ctrl_same_csr_outstanding 9.470s 545.632us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.770s 6034.017us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 219.610s 2564.214us 5 5 100.00
rom_ctrl_tl_intg_err 59.800s 816.351us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 219.610s 2564.214us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 219.610s 2564.214us 5 5 100.00
sec_cm_checker_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_checker_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_checker_fsm_local_esc 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_compare_ctrl_flow_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_compare_ctr_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 219.610s 2564.214us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 219.610s 2564.214us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.980s 329.922us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.980s 329.922us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.980s 329.922us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 59.800s 816.351us 20 20 100.00
sec_cm_bus_local_esc 17 22 77.27
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
rom_ctrl_kmac_err_chk 8.580s 545.402us 2 2 100.00
sec_cm_mux_mubi 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_mux_consistency 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_ctrl_redun 15 20 75.00
rom_ctrl_corrupt_sig_fatal_chk 108.360s 42234.250us 15 20 75.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.770s 6034.017us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 219.610s 2564.214us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 635.060s 5624.858us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 5 test runs
rom_ctrl_corrupt_sig_fatal_chk 2259289489104804083029659121901299902363369631041236121287460748285093057198 92
UVM_INFO @ 4541723026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 40548272158642699683986997820393382534679589374217247447643354347516504923496 83
UVM_INFO @ 542432533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 66748317471355458784924452639923419690121158453632941881821190777431163951880 96
UVM_INFO @ 3922379933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 14549778757473697751221864167777011429151166444306652095225907658769406664975 91
UVM_INFO @ 733598340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 50882840238910642986131433469169528383487006032673237412070032921992047142375 82
UVM_INFO @ 873546268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---