Simulation Results: rstmgr

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.830s 232.781us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.330s 146.621us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.280s 95.317us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 9.350s 2297.460us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.930s 354.241us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.670s 190.578us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.280s 95.317us 20 20 100.00
rstmgr_csr_aliasing 2.930s 354.241us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.420s 206.572us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 3.140s 493.374us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 2.090s 283.539us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 7.520s 1867.541us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 7.520s 1867.541us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 7.520s 1867.541us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 7.520s 1867.541us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 57.760s 12219.430us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.200s 72.739us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 4.330s 498.878us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 4.330s 498.878us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.330s 146.621us 5 5 100.00
rstmgr_csr_rw 1.280s 95.317us 20 20 100.00
rstmgr_csr_aliasing 2.930s 354.241us 5 5 100.00
rstmgr_same_csr_outstanding 1.990s 230.031us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.330s 146.621us 5 5 100.00
rstmgr_csr_rw 1.280s 95.317us 20 20 100.00
rstmgr_csr_aliasing 2.930s 354.241us 5 5 100.00
rstmgr_same_csr_outstanding 1.990s 230.031us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 26.350s 17324.003us 5 5 100.00
rstmgr_tl_intg_err 4.150s 955.131us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 26.350s 17324.003us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 26.350s 17324.003us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 4.150s 955.131us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.700s 181.112us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 7.790s 2249.372us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.790s 302.108us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 26.350s 17324.003us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.280s 95.317us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.280s 95.317us 20 20 100.00