| V1 |
|
100.00% |
| V2 |
|
92.50% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.440s | 815.957us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.840s | 18.173us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.890s | 14.996us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.250s | 1104.609us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.040s | 44.622us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.410s | 59.019us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.890s | 14.996us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.040s | 44.622us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 2 | 20 | 10.00 | |||
| rv_timer_random_reset | 3.430s | 10544.411us | 2 | 20 | 10.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.240s | 3143.894us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 451.880s | 1473128.736us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 451.880s | 1473128.736us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 21.050s | 9579.718us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.840s | 40.870us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.830s | 24.744us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.520s | 227.457us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.520s | 227.457us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.840s | 18.173us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.890s | 14.996us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.040s | 44.622us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.070s | 143.159us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.840s | 18.173us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.890s | 14.996us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.040s | 44.622us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.070s | 143.159us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.070s | 93.643us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.370s | 478.219us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.370s | 478.219us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 4 | 10 | 40.00 | |||
| rv_timer_min | 0.740s | 55.742us | 4 | 10 | 40.00 | |
| max_value | 0 | 10 | 0.00 | |||
| rv_timer_max | 1.130s | 43.193us | 0 | 10 | 0.00 | |
| stress_all_with_rand_reset | 16 | 20 | 80.00 | |||
| rv_timer_stress_all_with_rand_reset | 54.460s | 17340.035us | 16 | 20 | 80.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 24 test runs | |||
| rv_timer_min | 64801254720862398617926735368748822922420637066340477736434355335747492957945 | 75 |
UVM_INFO @ 224483154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 1983971469323908260177478164379096792314354385460364133981947362508445201125 | 75 |
UVM_INFO @ 100546692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 113734675036248105200150853105825199402493228792599119646517714343428631565971 | 76 |
UVM_INFO @ 236710037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 111223290568810748289028092782532214308186950433077319731422600223296347198524 | 75 |
UVM_INFO @ 225513801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50347525769093168633721626160582283593337945825951448905258489568116380160258 | 75 |
UVM_INFO @ 298479848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 78875656842232740233022500375440035348522883161247995299521812397943231539878 | 77 |
UVM_INFO @ 55741778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 106707629328351868724015121800342302958383125333212529045352886921943998794172 | 75 |
UVM_INFO @ 616390308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 35019715713714611581827779100116250238584084577476668738307965647884454866086 | 75 |
UVM_INFO @ 62956428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80490488395294898577502348973580277087231753079718338665226253659004815149636 | 75 |
UVM_INFO @ 253442554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50674471882352550538038880588956134672881396740267448885762148098256920000465 | 79 |
UVM_INFO @ 1760555748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 68466664807091206516139241603202957905695533817536405229735847478424054157388 | 77 |
UVM_INFO @ 290479251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 48532841958699963395547514307941820093881567160048884156095420486811050870710 | 75 |
UVM_INFO @ 502569620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 45789346323425220276321682837625808979982550904349064725207553930289915137669 | 75 |
UVM_INFO @ 394757787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 45593313858665122956769835444891082336026622531171256545674654522399283105282 | 75 |
UVM_INFO @ 124856829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 52787241675964120006374250666289422680227954598615497576684768108727246793914 | 78 |
UVM_INFO @ 237258668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 19060372378399361325752494316724303129246949889679778944465175372751217279752 | 75 |
UVM_INFO @ 316781598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 92435131192291322503864767016099369609883767076756748695142405416998181167868 | 75 |
UVM_INFO @ 227913063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 108470636595145257573075402795756633177090298567584314662107777145861510394347 | 75 |
UVM_INFO @ 125762268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 80033833972096195962935877608117450596686698883990750912894941929017657680536 | 75 |
UVM_INFO @ 129310847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 48932043605645812938603929669138763362964756558421265976663457091029751467872 | 75 |
UVM_INFO @ 254743469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50333548515280794262131547503691669274712264690581227185725123561459145021249 | 75 |
UVM_INFO @ 10544410564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 82769351038129555336007155927162477999063808492869734377958060243331277874894 | 75 |
UVM_INFO @ 266093615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42871282393332281811245340215193072485372909193209058100995047269930102815027 | 75 |
UVM_INFO @ 72415846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 56179996174890006566751730203325779425199399997474020157318238334437468557258 | 75 |
UVM_INFO @ 56704437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| rv_timer_max | 104749288464108383330150501961988615952416150646264048664288062652333109604787 | 77 |
UVM_INFO @ 44923466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 90616166159320919360624214144149049981460560572407854077742492008159939123111 | 75 |
UVM_INFO @ 392879778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 84398297387442527815517527403530780084146625672088368913716066333356073087374 | 77 |
UVM_INFO @ 188700530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 190147012331602033774172760987662224223963377660798524508200340310023643830 | 75 |
UVM_INFO @ 44739310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 71534209991475635584878292363862868779212364636198315468949130958242850068842 | 75 |
UVM_INFO @ 83369855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 79754065782053316993717880542095007771357434275189626328697477131991918765770 | 75 |
UVM_INFO @ 90950825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 63500808876863486002482803183165947711301361849964339946250695590295224037479 | 76 |
UVM_INFO @ 43647654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 40886001484853316626038360811187019877117932858552379579253033408262795683893 | 76 |
UVM_INFO @ 875783270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 31334546860607592565207709121441792623768574649687666195234213053277536967018 | 76 |
UVM_INFO @ 172610144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | 3 test runs | |||
| rv_timer_stress_all_with_rand_reset | 18246654490550285989300662229330309644004912504366294054142891366424107717853 | 254 |
UVM_INFO @ 26310529698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 84891638933900859449658131441668776482576788218338231585570660867015590982320 | 127 |
UVM_INFO @ 724737305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 111651712350273938926588584549849357516359461447361185734484727764693247375709 | 209 |
UVM_INFO @ 20844376630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 1 test run | |||
| rv_timer_stress_all_with_rand_reset | 81904744987966528127091238523501890781107781044170947326871721325863094607769 | 238 |
UVM_INFO @ 2282491362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 1 test run | |||
| rv_timer_max | 57298887948645073747869349244092812138142691944891631148293688410673518181427 | 75 |
UVM_INFO @ 43192672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|