Simulation Results

Simulation Results: spi_device/2p

09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.07 %

code
94.22 %

assert
94.74 %

func
99.26 %

line
98.96 %

branch
98.39 %

cond
96.65 %

toggle
87.74 %

FSM
89.36 %

Validation stages

V1		100.00%
V2		99.81%
V2S		100.00%
unmapped		98.00%

115/115 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	spi_device_flash_and_tpm	572.950s	78376.019us	50	50	100.00
csr_hw_reset				5	5	100.00
	spi_device_csr_hw_reset	1.850s	44.478us	5	5	100.00
csr_rw				20	20	100.00
	spi_device_csr_rw	3.190s	507.748us	20	20	100.00
csr_bit_bash				5	5	100.00
	spi_device_csr_bit_bash	35.710s	3759.913us	5	5	100.00
csr_aliasing				5	5	100.00
	spi_device_csr_aliasing	19.140s	2103.328us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	spi_device_csr_mem_rw_with_rand_reset	4.230s	892.684us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	spi_device_csr_rw	3.190s	507.748us	20	20	100.00
	spi_device_csr_aliasing	19.140s	2103.328us	5	5	100.00
mem_walk				5	5	100.00
	spi_device_mem_walk	1.050s	19.324us	5	5	100.00
mem_partial_access				5	5	100.00
	spi_device_mem_partial_access	2.650s	218.332us	5	5	100.00

1039/1041 passed

99.81 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				50	50	100.00
	spi_device_csb_read	1.190s	21.058us	50	50	100.00
mem_parity				20	20	100.00
	spi_device_mem_parity	1.540s	62.261us	20	20	100.00
mem_cfg				1	1	100.00
	spi_device_ram_cfg	1.130s	18.025us	1	1	100.00
tpm_read				50	50	100.00
	spi_device_tpm_rw	7.640s	225.910us	50	50	100.00
tpm_write				50	50	100.00
	spi_device_tpm_rw	7.640s	225.910us	50	50	100.00
tpm_hw_reg				100	100	100.00
	spi_device_tpm_read_hw_reg	21.770s	10730.952us	50	50	100.00
	spi_device_tpm_sts_read	1.340s	222.596us	50	50	100.00
tpm_fully_random_case				50	50	100.00
	spi_device_tpm_all	39.100s	32570.083us	50	50	100.00
pass_cmd_filtering				100	100	100.00
	spi_device_pass_cmd_filtering	41.430s	28289.026us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
pass_addr_translation				100	100	100.00
	spi_device_pass_addr_payload_swap	40.730s	9077.423us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
pass_payload_translation				100	100	100.00
	spi_device_pass_addr_payload_swap	40.730s	9077.423us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
cmd_info_slots				50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
cmd_read_status				100	100	100.00
	spi_device_intercept	25.310s	3170.836us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
cmd_read_jedec				100	100	100.00
	spi_device_intercept	25.310s	3170.836us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
cmd_read_sfdp				100	100	100.00
	spi_device_intercept	25.310s	3170.836us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
cmd_fast_read				100	100	100.00
	spi_device_intercept	25.310s	3170.836us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
cmd_read_pipeline				100	100	100.00
	spi_device_intercept	25.310s	3170.836us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
flash_cmd_upload				50	50	100.00
	spi_device_upload	38.820s	192660.013us	50	50	100.00
mailbox_command				50	50	100.00
	spi_device_mailbox	95.200s	13349.906us	50	50	100.00
mailbox_cross_outside_command				50	50	100.00
	spi_device_mailbox	95.200s	13349.906us	50	50	100.00
mailbox_cross_inside_command				50	50	100.00
	spi_device_mailbox	95.200s	13349.906us	50	50	100.00
cmd_read_buffer				100	100	100.00
	spi_device_flash_mode	51.200s	30369.807us	50	50	100.00
	spi_device_read_buffer_direct	18.550s	2195.009us	50	50	100.00
cmd_dummy_cycle				100	100	100.00
	spi_device_mailbox	95.200s	13349.906us	50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
quad_spi				50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
dual_spi				50	50	100.00
	spi_device_flash_all	327.520s	198481.689us	50	50	100.00
4b_3b_feature				50	50	100.00
	spi_device_cfg_cmd	24.540s	3654.227us	50	50	100.00
write_enable_disable				50	50	100.00
	spi_device_cfg_cmd	24.540s	3654.227us	50	50	100.00
TPM_with_flash_or_passthrough_mode				50	50	100.00
	spi_device_flash_and_tpm	572.950s	78376.019us	50	50	100.00
tpm_and_flash_trans_with_min_inactive_time				50	50	100.00
	spi_device_flash_and_tpm_min_idle	547.030s	351280.220us	50	50	100.00
stress_all				48	50	96.00
	spi_device_stress_all	809.320s	108453.958us	48	50	96.00
alert_test				50	50	100.00
	spi_device_alert_test	1.140s	12.945us	50	50	100.00
intr_test				50	50	100.00
	spi_device_intr_test	1.160s	55.886us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	spi_device_tl_errors	6.030s	229.499us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	spi_device_tl_errors	6.030s	229.499us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	spi_device_csr_hw_reset	1.850s	44.478us	5	5	100.00
	spi_device_csr_rw	3.190s	507.748us	20	20	100.00
	spi_device_csr_aliasing	19.140s	2103.328us	5	5	100.00
	spi_device_same_csr_outstanding	5.100s	1088.501us	20	20	100.00
tl_d_partial_access				50	50	100.00
	spi_device_csr_hw_reset	1.850s	44.478us	5	5	100.00
	spi_device_csr_rw	3.190s	507.748us	20	20	100.00
	spi_device_csr_aliasing	19.140s	2103.328us	5	5	100.00
	spi_device_same_csr_outstanding	5.100s	1088.501us	20	20	100.00

V2S

25/25 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	spi_device_sec_cm	1.680s	101.315us	5	5	100.00
	spi_device_tl_intg_err	22.260s	9518.345us	20	20	100.00
sec_cm_bus_integrity				20	20	100.00
	spi_device_tl_intg_err	22.260s	9518.345us	20	20	100.00

unmapped

49/50 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				49	50	98.00
	spi_device_flash_mode_ignore_cmds	402.520s	148181.280us	49	50	98.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (spi_device_scoreboard.sv:2512) [scoreboard] Check failed item.d_data == `gmv(csr) (* [] vs []) CSR last_read_addr compare mismatch act != exp *				2 test runs
	spi_device_stress_all	39153048322898708592895323020107250201117862820587628853160419901008886170658	112	UVM_INFO @ 37731363143 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 5/9 UVM_INFO @ 37731363143 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 6/9 tl_ul_fuzzy_flash_status_q[i] = 0x2c5ce8 tl_ul_fuzzy_flash_status_q[i] = 0x2c5ce8
	spi_device_stress_all	103874051817598477652094337222573878120317929134083712187475508642872181277894	122	UVM_INFO @ 181714894552 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 8/11 UVM_INFO @ 181714894552 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 9/11 tl_ul_fuzzy_flash_status_q[i] = 0xa91c10 tl_ul_fuzzy_flash_status_q[i] = 0xde9fe8
UVM_ERROR (spi_device_pass_base_vseq.sv:705) [spi_device_flash_mode_ignore_cmds_vseq] Check failed busy == * (* [] vs []) flash_status.busy == expected to be *				1 test run
	spi_device_flash_mode_ignore_cmds	106084196295928860944738583081664598713064366619363754521771314980484368002920	89	tl_ul_fuzzy_flash_status_q[i] = 0x1394a4 UVM_INFO @ 725457919 ps: (spi_device_flash_all_vseq.sv:72) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - END:running iteration 4/9 UVM_INFO @ 725457919 ps: (spi_device_flash_all_vseq.sv:51) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_mode_ignore_cmds_vseq] spi_device_env_pkg::\spi_device_flash_all_vseq::main_seq .unnamed$$_0 - running iteration 5/9 tl_ul_fuzzy_flash_status_q[i] = 0x5b2778