Simulation Results: spi_host

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.61%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 119.000s 10937.956us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 28.270us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 20.071us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 465.764us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 97.548us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 44.485us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 20.071us 20 20 100.00
spi_host_csr_aliasing 2.000s 97.548us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 19.491us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 1.000s 25.147us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 21.370us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 49.000s 8946.821us 50 50 100.00
spi_host_error_cmd 2.000s 17.604us 50 50 100.00
spi_host_event 670.000s 82922.629us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 7.000s 1784.211us 50 50 100.00
speed 50 50 100.00
spi_host_speed 7.000s 1784.211us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 7.000s 1784.211us 50 50 100.00
sw_reset 49 50 98.00
spi_host_sw_reset 197.000s 13211.944us 49 50 98.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 277.881us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 7.000s 1784.211us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 7.000s 1784.211us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 119.000s 10937.956us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 119.000s 10937.956us 50 50 100.00
stress_all 48 50 96.00
spi_host_stress_all 1886.000s 1000000.000us 48 50 96.00
spien 50 50 100.00
spi_host_spien 257.000s 28265.394us 50 50 100.00
stall 50 50 100.00
spi_host_status_stall 1743.000s 142513.479us 50 50 100.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 48.000s 20888.975us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 49.000s 8946.821us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 17.159us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 22.993us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 4.000s 535.065us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 4.000s 535.065us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 28.270us 5 5 100.00
spi_host_csr_rw 2.000s 20.071us 20 20 100.00
spi_host_csr_aliasing 2.000s 97.548us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 23.789us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 28.270us 5 5 100.00
spi_host_csr_rw 2.000s 20.071us 20 20 100.00
spi_host_csr_aliasing 2.000s 97.548us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 23.789us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 4.000s 3919.325us 20 20 100.00
spi_host_sec_cm 2.000s 287.472us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 4.000s 3919.325us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 10 10 100.00
spi_host_upper_range_clkdiv 896.000s 72067.081us 10 10 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
spi_host_stress_all 35272594128314560828261112727646370068393664603457540963730218799911139385546 372
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 32179619637215056459945417901892735478782047881770776317820996298105808109595 171
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_sw_reset 39103128181748680261464544193935887523149834429011704627418295306792989191678 138
UVM_INFO @ 10013791919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---