Simulation Results: sram_ctrl/main

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.67 %
  • code
  • 96.96 %
  • assert
  • 96.46 %
  • func
  • 96.60 %
  • block
  • 96.35 %
  • line
  • 97.11 %
  • branch
  • 94.65 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 12.000s 6954.142us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 231.049us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 39.791us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 47.041us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 48.864us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.000s 713.838us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 39.791us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 48.864us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 299.000s 147771.363us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 116.000s 18800.569us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 74.000s 33421.770us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 245.000s 6892.569us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 212.000s 201417.988us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 78.000s 13488.983us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 51.000s 15306.736us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 45.000s 13418.059us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 6.000s 1373.510us 5 5 100.00
sram_ctrl_partial_access_b2b 339.000s 99793.013us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 7.000s 1342.009us 5 5 100.00
sram_ctrl_throughput_w_partial_write 7.000s 4765.110us 5 5 100.00
sram_ctrl_throughput_w_readback 8.000s 4007.937us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 23.000s 3956.105us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 5.000s 706.480us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 483.000s 289366.579us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 46.968us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 7.000s 517.765us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 7.000s 517.765us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 231.049us 5 5 100.00
sram_ctrl_csr_rw 2.000s 39.791us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 48.864us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 18.902us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 231.049us 5 5 100.00
sram_ctrl_csr_rw 2.000s 39.791us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 48.864us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 18.902us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 46.000s 88172.652us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 6.000s 672.338us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 805.923us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 6.000s 672.338us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 805.923us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 23.000s 3956.105us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 23.000s 3956.105us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 39.791us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 45.000s 13418.059us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 45.000s 13418.059us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 45.000s 13418.059us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 51.000s 15306.736us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 1401.912us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 46.000s 88172.652us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 8.000s 1365.876us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 12.000s 6954.142us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 12.000s 6954.142us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 45.000s 13418.059us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 6.000s 672.338us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 51.000s 15306.736us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 6.000s 672.338us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 672.338us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 12.000s 6954.142us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 6.000s 672.338us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 73.000s 24466.237us 5 5 100.00