Simulation Results: sram_ctrl/ret

 
09/05/2026 22:36:56 DVSim: v1.34.0 sha: f3ee88d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.11 %
  • code
  • 83.49 %
  • assert
  • 96.43 %
  • func
  • 96.40 %
  • block
  • 94.01 %
  • line
  • 95.19 %
  • branch
  • 89.83 %
  • toggle
  • 82.28 %
  • FSM
  • 66.67 %
Validation stages
V1
98.57%
V2
100.00%
V2S
100.00%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 3.000s 57.131us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 19.210us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 18.203us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 479.827us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 77.712us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 28.775us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 18.203us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 77.712us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 12.000s 700.513us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 6.000s 168.205us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 20.000s 5359.434us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 226.000s 7309.397us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 8.000s 1123.041us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 24.000s 1562.397us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 7.000s 895.441us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 12.000s 4154.647us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 3.000s 47.778us 5 5 100.00
sram_ctrl_partial_access_b2b 375.000s 89229.672us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 2.000s 69.199us 5 5 100.00
sram_ctrl_throughput_w_partial_write 2.000s 147.321us 5 5 100.00
sram_ctrl_throughput_w_readback 2.000s 36.082us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 12.000s 198.856us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 2.000s 92.194us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 59.000s 14510.349us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 91.746us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 522.542us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 522.542us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 19.210us 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.203us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 77.712us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 100.787us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 19.210us 5 5 100.00
sram_ctrl_csr_rw 2.000s 18.203us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 77.712us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 100.787us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 698.540us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 4.000s 2066.540us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 278.262us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 4.000s 2066.540us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 278.262us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 12.000s 198.856us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 12.000s 198.856us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 18.203us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 12.000s 4154.647us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 12.000s 4154.647us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 12.000s 4154.647us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 7.000s 895.441us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 2.000s 53.632us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 5.000s 698.540us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 2.000s 48.660us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 57.131us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 3.000s 57.131us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 12.000s 4154.647us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 4.000s 2066.540us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 7.000s 895.441us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 4.000s 2066.540us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 2066.540us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 3.000s 57.131us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 4.000s 2066.540us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 5 80.00
sram_ctrl_stress_all_with_rand_reset 74.000s 6154.763us 4 5 80.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * 1 test run
sram_ctrl_csr_mem_rw_with_rand_reset 9242313007694764815102689143950183132456740371635967394748448645311605995247 94
UVM_INFO @ 28775088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1150) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
sram_ctrl_stress_all_with_rand_reset 93395461721311493835394401610936578068090813084660652961929529241260482413236 250
UVM_INFO @ 271183037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---