Simulation Results: aes/masked

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.64 %
  • code
  • 96.70 %
  • assert
  • 98.53 %
  • func
  • 97.68 %
  • block
  • 97.08 %
  • line
  • 98.21 %
  • branch
  • 92.75 %
  • toggle
  • 98.08 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.44%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 97.257us 1 1 100.00
smoke 50 50 100.00
aes_smoke 15.000s 600.114us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 27.000s 252.580us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 27.000s 71.660us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 32.000s 991.178us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 28.000s 493.796us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 27.000s 132.944us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 27.000s 71.660us 20 20 100.00
aes_csr_aliasing 28.000s 493.796us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 15.000s 600.114us 50 50 100.00
aes_config_error 28.000s 89.255us 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
key_length 150 150 100.00
aes_smoke 15.000s 600.114us 50 50 100.00
aes_config_error 28.000s 89.255us 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
back2back 100 100 100.00
aes_stress 19.000s 659.097us 50 50 100.00
aes_b2b 47.000s 698.794us 50 50 100.00
backpressure 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 15.000s 600.114us 50 50 100.00
aes_config_error 28.000s 89.255us 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
aes_alert_reset 29.000s 170.599us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 22.000s 152.379us 50 50 100.00
aes_config_error 28.000s 89.255us 50 50 100.00
aes_alert_reset 29.000s 170.599us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 60.000s 2360.656us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 32.000s 305.723us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 29.000s 170.599us 50 50 100.00
stress 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
sideload 100 100 100.00
aes_stress 19.000s 659.097us 50 50 100.00
aes_sideload 5.000s 327.585us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 27.000s 338.656us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 154.000s 7345.817us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 28.000s 57.257us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 643.797us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 643.797us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 27.000s 252.580us 5 5 100.00
aes_csr_rw 27.000s 71.660us 20 20 100.00
aes_csr_aliasing 28.000s 493.796us 5 5 100.00
aes_same_csr_outstanding 14.000s 342.822us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 27.000s 252.580us 5 5 100.00
aes_csr_rw 27.000s 71.660us 20 20 100.00
aes_csr_aliasing 28.000s 493.796us 5 5 100.00
aes_same_csr_outstanding 14.000s 342.822us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 49 50 98.00
aes_reseed 23.000s 1729.902us 49 50 98.00
fault_inject 662 700 94.57
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 10.000s 100.701us 19 20 95.00
tl_intg_err 25 25 100.00
aes_sec_cm 15.000s 2394.279us 5 5 100.00
aes_tl_intg_err 4.000s 252.002us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 252.002us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 29.000s 170.599us 50 50 100.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
sec_cm_main_config_sparse 217 220 98.64
aes_smoke 15.000s 600.114us 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
aes_alert_reset 29.000s 170.599us 50 50 100.00
aes_core_fi 35.000s 10011.001us 67 70 95.71
sec_cm_gcm_config_sparse 167 170 98.24
aes_config_error 28.000s 89.255us 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
aes_core_fi 35.000s 10011.001us 67 70 95.71
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 10.000s 154.381us 19 20 95.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 17.000s 72.283us 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 19.000s 659.097us 50 50 100.00
aes_sideload 5.000s 327.585us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 17.000s 72.283us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 17.000s 72.283us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 17.000s 72.283us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 17.000s 72.283us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 17.000s 72.283us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 19.000s 659.097us 50 50 100.00
sec_cm_main_fsm_sparse 49 50 98.00
aes_fi 28.000s 117.869us 49 50 98.00
sec_cm_main_fsm_redun 712 750 94.93
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 15.000s 149.702us 50 50 100.00
sec_cm_cipher_fsm_sparse 49 50 98.00
aes_fi 28.000s 117.869us 49 50 98.00
sec_cm_cipher_fsm_redun 662 700 94.57
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
sec_cm_cipher_ctr_redun 337 350 96.29
aes_cipher_fi 61.000s 0.000us 337 350 96.29
sec_cm_ctr_fsm_sparse 49 50 98.00
aes_fi 28.000s 117.869us 49 50 98.00
sec_cm_ctr_fsm_redun 375 400 93.75
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_ctr_fi 15.000s 149.702us 50 50 100.00
sec_cm_ghash_fsm_sparse 49 50 98.00
aes_fi 28.000s 117.869us 49 50 98.00
sec_cm_ctrl_sparse 712 750 94.93
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 15.000s 149.702us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 29.000s 170.599us 50 50 100.00
sec_cm_main_fsm_local_esc 712 750 94.93
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 15.000s 149.702us 50 50 100.00
sec_cm_cipher_fsm_local_esc 712 750 94.93
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
aes_ctr_fi 15.000s 149.702us 50 50 100.00
sec_cm_ctr_fsm_local_esc 375 400 93.75
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_ctr_fi 15.000s 149.702us 50 50 100.00
sec_cm_ghash_fsm_local_esc 49 50 98.00
aes_fi 28.000s 117.869us 49 50 98.00
sec_cm_data_reg_local_esc 662 700 94.57
aes_fi 28.000s 117.869us 49 50 98.00
aes_control_fi 61.000s 0.000us 276 300 92.00
aes_cipher_fi 61.000s 0.000us 337 350 96.29
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
aes_stress_all_with_rand_reset 126.000s 5977.402us 2 10 20.00

Error Messages

   Test seed line log context
Job timed out after * minutes 15 test runs
aes_control_fi 70323132457561447720617035874955705763599778360079539475115061746196153753277 None
aes_control_fi 35377466253403470935744582037013979745638229337973266503870728096750555182896 None
aes_control_fi 91829880703169545971684490687150680678593704618811529268741699154549269238284 None
aes_control_fi 29811096242458291847790749641659756148832978892534564245436174105864834507234 None
aes_cipher_fi 723171508620193345706737157153648841208982662746288347529172788694486494124 None
aes_control_fi 33676844461707042135733236161935272192142573897484563261724220044279973327755 None
aes_control_fi 103923370230736645977164711200587771405833285139506549919160189350541759612508 None
aes_control_fi 23010345405338482286698621689634876202313851198675584267944994312840492210363 None
aes_control_fi 110422907588339288312694557173889282247700417435276143222581019007778195268803 None
aes_control_fi 20175828739245635986093775483451657673616560817888508615227623528889988514107 None
aes_control_fi 13618454492670530852156961030322467350521189680107208997199920143308248447507 None
aes_control_fi 28500462724709658490595045523810643750992179320439064744761606004724825690924 None
aes_control_fi 11953661792119266197366383830974378118304183589352954314797680284075186294352 None
aes_control_fi 90742873523455596705508092749713681844152980602849380170797349415601991316324 None
aes_control_fi 63143290030205830140117908674730476494422291621770703458013055152054024300747 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 12 test runs
aes_cipher_fi 111803725050624824149023119384598475135834454794384508440767247366956722798351 149
UVM_INFO @ 10003063856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 76589312522350174925144616253356396169184601679702900945269468232357845058740 151
UVM_INFO @ 10006910753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 55647984622207825109152448573323709306631390155467849187020751810554462124430 143
UVM_INFO @ 10005691879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 32003390932449324217922681108337301777571304824427621912079354038116727220122 140
UVM_INFO @ 10003669835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 82925272623415645105999243063516916601610255667049982748376070943331761141508 146
UVM_INFO @ 10005435487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 31459833478284547332866198308337369087527996324045553128160376812898430279474 146
UVM_INFO @ 10094302208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57193858688195007259376262972652348999444172507771140002277384185533740074865 140
UVM_INFO @ 10060262620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 90442120842341438266526815701620231157355972040580880316224183856276349868312 154
UVM_INFO @ 10005806263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 71810691904759138023875498887164320934893233701674930918221557169680783290171 144
UVM_INFO @ 10002651803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 19145358814200488611653089755504420629770502425671593017615582606347863419984 140
UVM_INFO @ 10067496388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 29550602740606078364498612588671353009293286928437369130189512299767005596934 146
UVM_INFO @ 10007407276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25673413305880079284763852531870183504042702180010936295930139138875639222768 145
UVM_INFO @ 10004464388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 89512200718768168154901501001496714991524307558638438138264661403581950513231 148
UVM_INFO @ 10007615017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 110473339198314776101412833801927427102425103514791293219684847359406460392626 146
UVM_INFO @ 10046828926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 71263894567611490392320292663908684533892781920538963573324101170888756849827 147
UVM_INFO @ 10263113158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 76741375221804311545343372577298523480410427603728950815882434809860240161095 143
UVM_INFO @ 10012353267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 87161565232687076510008545240174242668836227256597308588343516014688434262854 149
UVM_INFO @ 10009502123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 18169422933587299627072653293958723122432810283903866430841099372320680255870 138
UVM_INFO @ 10020937861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 31095301133306726978840899414911271990234909867114997221369271505998961387713 139
UVM_INFO @ 10004721375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 28816388492214466497957037309941590294465260409209255558887781976409141990517 152
UVM_INFO @ 10009787275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 70501187192736264327628307620481842894140142065535418558456235807911679994451 141
UVM_INFO @ 10014061385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 31127755841030095531890687099001455686802431039599223485951694300780781520759 148
UVM_INFO @ 10005025979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 23129166497739550276431046696537012113834384441361052564390873992917346649926 206
UVM_INFO @ 385433569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 90468001360342998738625460940581475160214150059196654237509996885157506206001 159
UVM_INFO @ 253431807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 40632794108347000179004992546812202937097643886255014453588226423003231120180 166
UVM_INFO @ 50373140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 109458735944378508382912653062668194192570727639625612909438128369055799431729 1066
UVM_INFO @ 624288636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 59412108090261569515097065756847448726938068382231085256297555505147387076491 226
UVM_INFO @ 736690649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 70731798244530843042325060194103316942713506232795787676386224739088578024853 453
UVM_INFO @ 154026162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 3 test runs
aes_core_fi 321213276178479821344371882880998937084169484867804295637300240977532634452 140
UVM_INFO @ 10066026949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 115118324500933791420347896616439592714279645764454492678528132757906792154543 143
UVM_INFO @ 10011001021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 12383015190650420956942368826934535609854064960103155478733509289727707393129 142
UVM_INFO @ 10012297956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
aes_stress_all_with_rand_reset 15670212542072838692846352356893310945280453249195232639695070198433619654178 1347
UVM_INFO @ 9020010716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 13689836242498503530316612643983537225211775794051766245638505437419381055097 544
UVM_INFO @ 1758319307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_reseed 70782502151204196062313336971369147651203029240227824458138026455896716958287 1378
TEST FAILED MESSAGES DID NOT MATCH
0 3a af a8 0
1 00 f0 40 0
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 1 test run
aes_shadow_reg_errors_with_csr_rw 51175617870625710505660269427304536786222504035666934915186004985225034350120 107
UVM_INFO @ 10706769918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 65813670246769236457634367837622239980993235235744019285413055618798725077837 106
UVM_INFO @ 24517522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:95) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset 1 test run
aes_fi 104330466352681868913986716455774498882723876419585660634635149664241199996773 25031
UVM_INFO @ 55039602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---