Simulation Results: aes/unmasked

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.93 %
  • code
  • 93.15 %
  • assert
  • 98.11 %
  • func
  • 96.52 %
  • block
  • 94.23 %
  • line
  • 96.00 %
  • branch
  • 87.50 %
  • toggle
  • 97.99 %
  • FSM
  • 91.11 %
Validation stages
V1
100.00%
V2
99.66%
V2S
95.30%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 72.722us 1 1 100.00
smoke 50 50 100.00
aes_smoke 4.000s 188.325us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 2.000s 55.534us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 2.000s 96.173us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 6.000s 186.900us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 616.825us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 84.935us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 2.000s 96.173us 20 20 100.00
aes_csr_aliasing 3.000s 616.825us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 4.000s 188.325us 50 50 100.00
aes_config_error 3.000s 83.523us 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
key_length 150 150 100.00
aes_smoke 4.000s 188.325us 50 50 100.00
aes_config_error 3.000s 83.523us 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 111.800us 50 50 100.00
aes_b2b 7.000s 154.671us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
multi_message 199 200 99.50
aes_smoke 4.000s 188.325us 50 50 100.00
aes_config_error 3.000s 83.523us 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
aes_alert_reset 4.000s 306.999us 49 50 98.00
failure_test 149 150 99.33
aes_man_cfg_err 3.000s 83.845us 50 50 100.00
aes_config_error 3.000s 83.523us 50 50 100.00
aes_alert_reset 4.000s 306.999us 49 50 98.00
trigger_clear_test 50 50 100.00
aes_clear 4.000s 70.675us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 485.145us 1 1 100.00
reset_recovery 49 50 98.00
aes_alert_reset 4.000s 306.999us 49 50 98.00
stress 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 111.800us 50 50 100.00
aes_sideload 4.000s 282.130us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 4.000s 652.673us 50 50 100.00
stress_all 9 10 90.00
aes_stress_all 25.000s 575.106us 9 10 90.00
alert_test 50 50 100.00
aes_alert_test 3.000s 64.738us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 216.819us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 216.819us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 2.000s 55.534us 5 5 100.00
aes_csr_rw 2.000s 96.173us 20 20 100.00
aes_csr_aliasing 3.000s 616.825us 5 5 100.00
aes_same_csr_outstanding 3.000s 131.796us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 2.000s 55.534us 5 5 100.00
aes_csr_rw 2.000s 96.173us 20 20 100.00
aes_csr_aliasing 3.000s 616.825us 5 5 100.00
aes_same_csr_outstanding 3.000s 131.796us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 49 50 98.00
aes_reseed 4.000s 276.125us 49 50 98.00
fault_inject 655 700 93.57
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
shadow_reg_update_error 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
shadow_reg_read_clear_staged_value 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
shadow_reg_storage_error 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
shadowed_reset_glitch 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 8.000s 10046.424us 19 20 95.00
tl_intg_err 25 25 100.00
aes_sec_cm 7.000s 2853.931us 5 5 100.00
aes_tl_intg_err 3.000s 193.590us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 3.000s 193.590us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 49 50 98.00
aes_alert_reset 4.000s 306.999us 49 50 98.00
sec_cm_main_config_shadow 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
sec_cm_gcm_config_shadow 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
sec_cm_main_config_sparse 211 220 95.91
aes_smoke 4.000s 188.325us 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
aes_alert_reset 4.000s 306.999us 49 50 98.00
aes_core_fi 139.000s 10020.459us 62 70 88.57
sec_cm_gcm_config_sparse 162 170 95.29
aes_config_error 3.000s 83.523us 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
aes_core_fi 139.000s 10020.459us 62 70 88.57
sec_cm_aux_config_shadow 18 20 90.00
aes_shadow_reg_errors 7.000s 10003.771us 18 20 90.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 100.950us 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 111.800us 50 50 100.00
aes_sideload 4.000s 282.130us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 100.950us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 100.950us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 100.950us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 100.950us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 100.950us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 111.800us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 4.000s 213.209us 50 50 100.00
sec_cm_main_fsm_redun 705 750 94.00
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
aes_ctr_fi 3.000s 50.484us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 4.000s 213.209us 50 50 100.00
sec_cm_cipher_fsm_redun 655 700 93.57
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
sec_cm_cipher_ctr_redun 328 350 93.71
aes_cipher_fi 62.031s 0.000us 328 350 93.71
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 4.000s 213.209us 50 50 100.00
sec_cm_ctr_fsm_redun 377 400 94.25
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_ctr_fi 3.000s 50.484us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 4.000s 213.209us 50 50 100.00
sec_cm_ctrl_sparse 705 750 94.00
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
aes_ctr_fi 3.000s 50.484us 50 50 100.00
sec_cm_main_fsm_global_esc 49 50 98.00
aes_alert_reset 4.000s 306.999us 49 50 98.00
sec_cm_main_fsm_local_esc 705 750 94.00
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
aes_ctr_fi 3.000s 50.484us 50 50 100.00
sec_cm_cipher_fsm_local_esc 705 750 94.00
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
aes_ctr_fi 3.000s 50.484us 50 50 100.00
sec_cm_ctr_fsm_local_esc 377 400 94.25
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_ctr_fi 3.000s 50.484us 50 50 100.00
sec_cm_ghash_fsm_local_esc 50 50 100.00
aes_fi 4.000s 213.209us 50 50 100.00
sec_cm_data_reg_local_esc 655 700 93.57
aes_fi 4.000s 213.209us 50 50 100.00
aes_control_fi 61.000s 0.000us 277 300 92.33
aes_cipher_fi 62.031s 0.000us 328 350 93.71
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
aes_stress_all_with_rand_reset 47.000s 1621.059us 1 10 10.00

Error Messages

   Test seed line log context
Job timed out after * minutes 28 test runs
aes_cipher_fi 60159821335315733731494079230606719820587715621548709239110631966303457433007 None
aes_control_fi 82708888525319582319772292140636334462357722352205620799137028115534012563102 None
aes_cipher_fi 97215202889925276374374300054212123307786129301560157110197298120115814642195 None
aes_control_fi 29907375585300423293199443925190091013300889114282996046663019909644081923274 None
aes_control_fi 111262410613231288636222246120832127053561103371657103158440907593185461390585 None
aes_cipher_fi 3003255988443399380890704206438378985240694077057416839332557791697805092288 None
aes_control_fi 73877643682069788487982545415754270024506257503619721455630840920695287807045 None
aes_cipher_fi 6079821489756341578967943813377846877992608189964691122534796188568889668925 None
aes_cipher_fi 56062765741451583050351787873560364776689247659646343483086880039327730566471 None
aes_cipher_fi 102712711973678651657528312300614792801011769990841647535284213889337310857551 None
aes_cipher_fi 29964398292376975614195487980814082877087674142422063177660518796654628651209 None
aes_control_fi 99664580065927760183288866655341367765576635268812749649179430421175626250919 None
aes_control_fi 4120097732016689338565124948805417185470992685771086155511988156009129161162 None
aes_control_fi 92574875605489402901839227478761916723354527963602465376830949704286620805233 None
aes_control_fi 85947787310260305375674594145631875450775217683577049753023578617418318733647 None
aes_cipher_fi 16029564977951764906931331627310546011743971405374589927019645993788996544583 None
aes_cipher_fi 103291484958525762680850849912772539664439556302388009018190937404357930722546 None
aes_cipher_fi 16470495570627467599560735860910933613552802637730449329213521321327605333015 None
aes_cipher_fi 111443036859831521343237199049783518076892683982187991341850655891786133422558 None
aes_control_fi 67748366727552589941357856878222730773151956897039019026237188899224093721441 None
aes_control_fi 68004292780659597503831541744493469298947439085551062379641694692616867765509 None
aes_control_fi 18308076175507841697992879601222848411054856590344774199084032009361084626858 None
aes_control_fi 71295366477525368621570644033203400216091570478019180851531734106821885385238 None
aes_control_fi 47561308512515482486230766565787164606178860632372962844613389153740232248100 None
aes_cipher_fi 36641986874057490254423856162840633242879612558674693699863066385836346148876 None
aes_cipher_fi 99392101322998251020151319330566166805741687264296158788633835982017849087700 None
aes_cipher_fi 66709599120116330650374353456913623494842588919739692915220270922399412702578 None
aes_cipher_fi 31967488712107508369130864886170657555079256686132405952254304363920956630810 None
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 10 test runs
aes_control_fi 8305557481258672264373894786547510766330467428177114636627754930673686211536 141
UVM_INFO @ 10002588172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 61266072141406064260517752850881332420946824330450394350540934399640823591032 146
UVM_INFO @ 10004794250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 29828184998261455282446000097034530222501462499483131378421993420144006859667 150
UVM_INFO @ 10005201583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 37255443456512421734338878811364138552804220611712445823264963706797956294919 151
UVM_INFO @ 10004205013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 47736217469230550689719409687348300856508946129035260679131977471176051743530 141
UVM_INFO @ 10012443636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 71629206018480692016075928197943273779246649444214201084812727975398547518274 139
UVM_INFO @ 10006989207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86712941592182675261290327573034931106925597698064627483732625930764123027865 152
UVM_INFO @ 10017503402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90905267340880056926944440338475534315373030036538403918487123762863215411258 146
UVM_INFO @ 10003694905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 58491522191787828052468038683206549116027099995308029905589193092806781534437 141
UVM_INFO @ 10020469308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 87465560424670543116475054331134078805931104431652724132266103667411023457084 142
UVM_INFO @ 10004810017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 7 test runs
aes_cipher_fi 29427026336350273058064658837855094878041531248372476311183872945733216211768 147
UVM_INFO @ 10093406861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 51237831892049102296374177329947317948057828560608331461234418606201360617360 152
UVM_INFO @ 10005517547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 80109419485412442625148378488643571713650809554433838047596487051692327158457 143
UVM_INFO @ 10004169299 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 63353078269858037641885180039332554597756725508926121252878224201379986379258 144
UVM_INFO @ 10021442901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 106275034465725160030951684435464160072855535190021575611840563508064460107501 148
UVM_INFO @ 10004707047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 70307061382816197702626408181508549562251363680218490863563384483393655736669 149
UVM_INFO @ 10003347389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 90991960317873749749867616633492689063260360518530862943344725821877198402789 141
UVM_INFO @ 10004028857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 5 test runs
aes_core_fi 21550287914722983911103311522528586336356344487313709839880499708222659307011 148
UVM_INFO @ 10008711424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 39861020149357119062467116635022086919692719917739964725603276752282139399885 148
UVM_INFO @ 10016590807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 50450232465307605893025227626054629733364175315920093028941146610686366297777 145
UVM_INFO @ 10004663934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 1219346699004905759675987188045904720939996323837805749448302806058007964800 151
UVM_INFO @ 10004382147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 69456019276260782620358009431432057223977883226440825992882485854068574006737 139
UVM_INFO @ 10003682914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 43360475458394802693367708282786889832563086147593833384770095968404397318418 244
UVM_INFO @ 522688534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 54101014192581501571342190790919433514720114415950600242596675313867783778842 166
UVM_INFO @ 69967490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 107999631877764442648031878108536636588686245187686367539475541935490196670241 347
UVM_INFO @ 99654272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_stress_all_with_rand_reset 40972265679408337769184158383313446031822327364827763071227444361113239711333 456
UVM_INFO @ 332735038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 113193697488688734828818548128767473272780145672976062392331275316039358919917 1583
UVM_INFO @ 1798829515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 70634019902177650913727997330152125027369407365810798730826922714208836362862 1001
UVM_INFO @ 5341758630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq__shadow_reg_errors.svh:336) [aes_common_vseq] ctrl_shadowed update_err alert timeout 2 test runs
aes_shadow_reg_errors 53146285199651990655377650703804005909359616652540812188709988182926058648836 106
UVM_INFO @ 10003771243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_shadow_reg_errors_with_csr_rw 62970830632846079047336459134334208648390353925882119601778543971245875433862 106
UVM_INFO @ 10046423684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 54620908191373811022144028695802951408665724456156835581895896212654955283440 932
UVM_INFO @ 1810099999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 106000091435053103233043160058315815369628234270598461640163112145621665423312 173
UVM_INFO @ 141640737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_aes_*/rtl/aes_core.sv,1142): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) 1 test run
aes_stress_all 108743103846323598455164702970702205461069806914936162503080869826456341353474 14257
UVM_ERROR @ 61693433 ps: (aes_core.sv:1142) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
UVM_INFO @ 61693433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 1 test run
aes_alert_reset 85560211722744670155634271217547380177391913505704419795716120004923392647196 906
UVM_INFO @ 37898286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 90256763256205996527107101992534663317965785964233075933557242893994909502653 1357
UVM_INFO @ 2334758921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 39847414476613138505419997779259812349075677001677752181485798731208204042930 106
UVM_INFO @ 40098231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_reseed 92187761804027584226639085632628176431147971618181568677538139779664657477853 1291
TEST FAILED MESSAGES DID NOT MATCH
0 fd e9 4f 0
1 00 00 a0 0
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) 1 test run
aes_core_fi 47717082204405480260489195262260610252282639549494333476878105366788984601467 149
UVM_INFO @ 10019217904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 83310893401071038130050048023788109488445725241959950159939314589993708670316 142
UVM_INFO @ 10020458857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
aes_core_fi 108156690136910272100344123830960467408006640204684704939612356459228026292449 144
UVM_INFO @ 10035624459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---