| V1 |
|
93.64% |
| V2 |
|
90.84% |
| V2S |
|
83.33% |
| V3 |
|
88.05% |
| unmapped |
|
58.06% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 12 | 12 | 100.00 | |||
| chip_sw_example_flash | 244.330s | 3276.949us | 3 | 3 | 100.00 | |
| chip_sw_example_rom | 127.750s | 3110.539us | 3 | 3 | 100.00 | |
| chip_sw_example_manufacturer | 239.920s | 3265.153us | 3 | 3 | 100.00 | |
| chip_sw_example_concurrency | 230.710s | 3357.727us | 3 | 3 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| chip_csr_hw_reset | 345.030s | 6318.235us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| chip_csr_rw | 663.160s | 5808.486us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| chip_csr_bit_bash | 5685.610s | 59292.216us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| chip_csr_aliasing | 7320.970s | 41174.181us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 6 | 20 | 30.00 | |||
| chip_csr_mem_rw_with_rand_reset | 736.140s | 9964.125us | 6 | 20 | 30.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| chip_csr_aliasing | 7320.970s | 41174.181us | 5 | 5 | 100.00 | |
| chip_csr_rw | 663.160s | 5808.486us | 20 | 20 | 100.00 | |
| xbar_smoke | 100 | 100 | 100.00 | |||
| xbar_smoke | 12.130s | 237.959us | 100 | 100 | 100.00 | |
| chip_sw_gpio_out | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 424.240s | 4865.966us | 3 | 3 | 100.00 | |
| chip_sw_gpio_in | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 424.240s | 4865.966us | 3 | 3 | 100.00 | |
| chip_sw_gpio_irq | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 424.240s | 4865.966us | 3 | 3 | 100.00 | |
| chip_sw_uart_tx_rx | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 511.590s | 4706.829us | 5 | 5 | 100.00 | |
| chip_sw_uart_rx_overflow | 20 | 20 | 100.00 | |||
| chip_sw_uart_tx_rx | 511.590s | 4706.829us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx1 | 545.750s | 4330.609us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx2 | 520.120s | 4149.713us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx3 | 460.340s | 4704.979us | 5 | 5 | 100.00 | |
| chip_sw_uart_baud_rate | 20 | 20 | 100.00 | |||
| chip_sw_uart_rand_baudrate | 2590.980s | 13877.005us | 20 | 20 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 10 | 10 | 100.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 2348.110s | 12726.888us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 947.220s | 9467.050us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 297.620s | 5163.911us | 10 | 10 | 100.00 | |
| chip_padctrl_attributes | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 297.620s | 5163.911us | 10 | 10 | 100.00 | |
| chip_sw_sleep_pin_mio_dio_val | 2 | 3 | 66.67 | |||
| chip_sw_sleep_pin_mio_dio_val | 288.030s | 4026.027us | 2 | 3 | 66.67 | |
| chip_sw_sleep_pin_wake | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_wake | 360.080s | 6531.616us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pin_retention | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_retention | 236.170s | 3872.734us | 3 | 3 | 100.00 | |
| chip_sw_tap_strap_sampling | 20 | 20 | 100.00 | |||
| chip_tap_straps_dev | 1383.360s | 15858.106us | 5 | 5 | 100.00 | |
| chip_tap_straps_testunlock0 | 397.180s | 6315.967us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 633.870s | 7110.863us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1442.200s | 10965.183us | 5 | 5 | 100.00 | |
| chip_sw_pattgen_ios | 3 | 3 | 100.00 | |||
| chip_sw_pattgen_ios | 191.590s | 2688.436us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pwm_pulses | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pwm_pulses | 959.780s | 8802.308us | 3 | 3 | 100.00 | |
| chip_sw_data_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 645.170s | 5636.042us | 6 | 6 | 100.00 | |
| chip_sw_instruction_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 645.170s | 5636.042us | 6 | 6 | 100.00 | |
| chip_sw_ast_clk_outputs | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 858.830s | 8542.628us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 1504.010s | 13271.469us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 460.310s | 4626.982us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 816.220s | 6258.839us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4654.810s | 18604.632us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 249.730s | 3475.479us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1095.140s | 8584.150us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 258.110s | 3340.337us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2202.160s | 12771.098us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 295.950s | 3036.856us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 449.160s | 5439.348us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 213.560s | 2514.378us | 3 | 3 | 100.00 | |
| chip_sw_ast_usb_clk_calib | 1 | 1 | 100.00 | |||
| chip_sw_usb_ast_clk_calib | 240.890s | 3281.354us | 1 | 1 | 100.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 6 | 8 | 75.00 | |||
| chip_sw_sensor_ctrl_alert | 626.700s | 9116.833us | 3 | 5 | 60.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 343.820s | 5022.473us | 3 | 3 | 100.00 | |
| chip_sw_sensor_ctrl_ast_status | 3 | 3 | 100.00 | |||
| chip_sw_sensor_ctrl_status | 261.090s | 3336.548us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 343.820s | 5022.473us | 3 | 3 | 100.00 | |
| chip_sw_smoketest | 51 | 51 | 100.00 | |||
| chip_sw_flash_scrambling_smoketest | 206.180s | 3054.593us | 3 | 3 | 100.00 | |
| chip_sw_aes_smoketest | 239.910s | 3830.464us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_smoketest | 324.090s | 3501.124us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_smoketest | 217.880s | 3467.720us | 3 | 3 | 100.00 | |
| chip_sw_csrng_smoketest | 274.970s | 3126.899us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_smoketest | 1245.780s | 7504.521us | 3 | 3 | 100.00 | |
| chip_sw_gpio_smoketest | 219.470s | 2664.085us | 3 | 3 | 100.00 | |
| chip_sw_hmac_smoketest | 307.480s | 3746.710us | 3 | 3 | 100.00 | |
| chip_sw_kmac_smoketest | 292.690s | 3414.995us | 3 | 3 | 100.00 | |
| chip_sw_otbn_smoketest | 1832.430s | 10670.695us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 460.330s | 5871.249us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 322.900s | 5533.294us | 3 | 3 | 100.00 | |
| chip_sw_rv_plic_smoketest | 256.860s | 3839.400us | 3 | 3 | 100.00 | |
| chip_sw_rv_timer_smoketest | 273.570s | 3572.395us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_smoketest | 238.260s | 3292.600us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 240.180s | 2807.930us | 3 | 3 | 100.00 | |
| chip_sw_uart_smoketest | 234.070s | 2747.065us | 3 | 3 | 100.00 | |
| chip_sw_otp_smoketest | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_smoketest | 219.820s | 3014.162us | 3 | 3 | 100.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 436.250s | 4289.129us | 0 | 3 | 0.00 | |
| chip_sw_boot | 3 | 3 | 100.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 12227.000s | 62866.791us | 3 | 3 | 100.00 | |
| chip_sw_secure_boot | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3992.900s | 14878.647us | 3 | 3 | 100.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 56.350s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 319.440s | 3983.015us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 276.060s | 3593.420us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 3 | 3 | 100.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 11368.920s | 56058.938us | 3 | 3 | 100.00 | |
| chip_sw_inject_scramble_seed | 3 | 3 | 100.00 | |||
| chip_sw_inject_scramble_seed | 11450.110s | 57558.194us | 3 | 3 | 100.00 | |
| tl_d_oob_addr_access | 3 | 30 | 10.00 | |||
| chip_tl_errors | 227.590s | 3234.340us | 3 | 30 | 10.00 | |
| tl_d_illegal_access | 3 | 30 | 10.00 | |||
| chip_tl_errors | 227.590s | 3234.340us | 3 | 30 | 10.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| chip_csr_aliasing | 7320.970s | 41174.181us | 5 | 5 | 100.00 | |
| chip_same_csr_outstanding | 4419.270s | 26770.737us | 20 | 20 | 100.00 | |
| chip_csr_hw_reset | 345.030s | 6318.235us | 5 | 5 | 100.00 | |
| chip_csr_rw | 663.160s | 5808.486us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| chip_csr_aliasing | 7320.970s | 41174.181us | 5 | 5 | 100.00 | |
| chip_same_csr_outstanding | 4419.270s | 26770.737us | 20 | 20 | 100.00 | |
| chip_csr_hw_reset | 345.030s | 6318.235us | 5 | 5 | 100.00 | |
| chip_csr_rw | 663.160s | 5808.486us | 20 | 20 | 100.00 | |
| xbar_base_random_sequence | 100 | 100 | 100.00 | |||
| xbar_random | 89.270s | 2847.836us | 100 | 100 | 100.00 | |
| xbar_random_delay | 600 | 600 | 100.00 | |||
| xbar_smoke_zero_delays | 8.600s | 55.657us | 100 | 100 | 100.00 | |
| xbar_smoke_large_delays | 108.520s | 10297.362us | 100 | 100 | 100.00 | |
| xbar_smoke_slow_rsp | 99.870s | 6942.725us | 100 | 100 | 100.00 | |
| xbar_random_zero_delays | 52.850s | 596.701us | 100 | 100 | 100.00 | |
| xbar_random_large_delays | 480.920s | 57522.729us | 100 | 100 | 100.00 | |
| xbar_random_slow_rsp | 467.530s | 35462.784us | 100 | 100 | 100.00 | |
| xbar_unmapped_address | 200 | 200 | 100.00 | |||
| xbar_unmapped_addr | 53.600s | 1527.135us | 100 | 100 | 100.00 | |
| xbar_error_and_unmapped_addr | 53.990s | 1374.706us | 100 | 100 | 100.00 | |
| xbar_error_cases | 200 | 200 | 100.00 | |||
| xbar_error_random | 82.570s | 2216.932us | 100 | 100 | 100.00 | |
| xbar_error_and_unmapped_addr | 53.990s | 1374.706us | 100 | 100 | 100.00 | |
| xbar_all_access_same_device | 200 | 200 | 100.00 | |||
| xbar_access_same_device | 123.320s | 3418.587us | 100 | 100 | 100.00 | |
| xbar_access_same_device_slow_rsp | 1152.900s | 93280.701us | 100 | 100 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 100 | 100 | 100.00 | |||
| xbar_same_source | 86.400s | 2740.159us | 100 | 100 | 100.00 | |
| xbar_stress_all | 200 | 200 | 100.00 | |||
| xbar_stress_all | 708.770s | 22858.757us | 100 | 100 | 100.00 | |
| xbar_stress_all_with_error | 716.310s | 23601.018us | 100 | 100 | 100.00 | |
| xbar_stress_with_reset | 200 | 200 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 688.880s | 18590.644us | 100 | 100 | 100.00 | |
| xbar_stress_all_with_reset_error | 897.640s | 25048.478us | 100 | 100 | 100.00 | |
| rom_e2e_smoke | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3992.900s | 14878.647us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_output | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_output | 3405.040s | 27145.744us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_exception_c | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_exception_c | 4018.590s | 15646.556us | 3 | 3 | 100.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 68.491s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 8.530s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 26.881s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 24.908s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 37.828s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 82.720s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 20.644s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 59.973s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 11.255s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 21.698s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 88.118s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 38.654s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 74.814s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 71.516s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 33.523s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 30.800s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 21.800s | 10.240us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 33.040s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 23.050s | 10.120us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 25.540s | 10.100us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 21.570s | 10.340us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 20.970s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 24.120s | 10.140us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 25.680s | 10.260us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 30.880s | 10.160us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 20.260s | 10.400us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 32.750s | 10.380us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 32.690s | 10.160us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 21.360s | 10.380us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 18.510s | 10.180us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 96.795s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 62.846s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 43.411s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 24.176s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 52.607s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 5 | 9 | 55.56 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 7720.470s | 31263.477us | 3 | 3 | 100.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 3965.290s | 16384.021us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 7823.760s | 28814.034us | 2 | 3 | 66.67 | |
| rom_e2e_static_critical | 3 | 3 | 100.00 | |||
| rom_e2e_static_critical | 4142.970s | 16258.744us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.182s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.182s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 6 | 6 | 100.00 | |||
| chip_sw_aes_enc | 274.650s | 3376.503us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 249.730s | 3475.479us | 3 | 3 | 100.00 | |
| chip_sw_aes_entropy | 3 | 3 | 100.00 | |||
| chip_sw_aes_entropy | 198.630s | 3167.283us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 3 | 3 | 100.00 | |||
| chip_sw_aes_idle | 200.910s | 2420.370us | 3 | 3 | 100.00 | |
| chip_sw_aes_sideload | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 1686.130s | 10713.013us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 282.280s | 3668.811us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 457.690s | 5610.734us | 3 | 3 | 100.00 | |
| chip_sw_all_escalation_resets | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| chip_sw_alert_handler_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 780.310s | 5465.998us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 393.120s | 4465.376us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 521.810s | 4464.835us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_entropy | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_entropy | 307.880s | 3467.961us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_crashdump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1615.020s | 12457.156us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_timeout | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 445.400s | 5794.422us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 277.880s | 3562.334us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 14400.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1627.060s | 9536.979us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1471.760s | 7924.828us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_ok | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_ok | 1051.260s | 8110.096us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 13798.170s | 255711.968us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 335.590s | 3619.904us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_smoketest | 460.330s | 5871.249us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 335.590s | 3619.904us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 1 | 3 | 33.33 | |||
| chip_sw_aon_timer_wdog_bite_reset | 754.880s | 8680.251us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 1 | 3 | 33.33 | |||
| chip_sw_aon_timer_wdog_bite_reset | 754.880s | 8680.251us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 5 | 5 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 399.880s | 7177.902us | 5 | 5 | 100.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 543.840s | 4660.887us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 12 | 12 | 100.00 | |||
| chip_sw_otbn_randomness | 801.000s | 6502.918us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 200.910s | 2420.370us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_idle | 235.380s | 2889.049us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 214.820s | 2675.149us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_trans | 12 | 12 | 100.00 | |||
| chip_sw_clkmgr_off_aes_trans | 395.190s | 5158.118us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_hmac_trans | 427.800s | 5004.387us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_kmac_trans | 377.050s | 4950.908us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_otbn_trans | 296.410s | 3984.505us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_peri | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_off_peri | 998.900s | 12796.340us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_div | 21 | 21 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 480.570s | 4406.734us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 543.510s | 5104.762us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 526.900s | 4275.521us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 535.650s | 5630.403us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 525.390s | 4438.191us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 499.800s | 4968.209us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_outputs | 858.830s | 8542.628us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 473.870s | 7162.236us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 6 | 6 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 526.900s | 4275.521us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 535.650s | 5630.403us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 460.310s | 4626.982us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 816.220s | 6258.839us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4654.810s | 18604.632us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 249.730s | 3475.479us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1095.140s | 8584.150us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 258.110s | 3340.337us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2202.160s | 12771.098us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 295.950s | 3036.856us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 449.160s | 5439.348us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 213.560s | 2514.378us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_extended_range | 33 | 33 | 100.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 183.900s | 3171.804us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 516.190s | 5308.364us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 878.610s | 7981.153us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 5141.690s | 25442.264us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 288.530s | 3241.312us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 239.090s | 3517.241us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 1291.380s | 10847.637us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 269.210s | 3525.138us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 504.190s | 5189.160us | 3 | 3 | 100.00 | |
| chip_sw_flash_init_reduced_freq | 1582.430s | 24649.201us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 25059.740s | 155815.314us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 858.830s | 8542.628us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_sleep_frequency | 503.960s | 4889.255us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_reset_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_reset_frequency | 371.280s | 3720.595us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_escalation_reset | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1627.060s | 9536.979us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_cmd | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3067.060s | 24010.831us | 3 | 3 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 1 | 3 | 33.33 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 319.910s | 4549.247us | 1 | 3 | 33.33 | |
| chip_sw_csrng_lc_hw_debug_en | 3 | 3 | 100.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 614.400s | 7664.157us | 3 | 3 | 100.00 | |
| chip_sw_csrng_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_csrng_kat_test | 273.940s | 3223.302us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 16 | 16 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 9872.840s | 44263.339us | 10 | 10 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 236.440s | 3589.327us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1017.760s | 6342.803us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_ast_rng_req | 236.440s | 3589.327us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_csrng | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3067.060s | 24010.831us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_kat_test | 238.220s | 2911.505us | 3 | 3 | 100.00 | |
| chip_sw_flash_init | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1783.660s | 18130.844us | 3 | 3 | 100.00 | |
| chip_sw_flash_host_access | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_access | 794.110s | 5776.686us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 816.220s | 6258.839us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_ops | 457.180s | 4355.547us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 460.310s | 4626.982us | 3 | 3 | 100.00 | |
| chip_sw_flash_rma_unlocked | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4942.010s | 43330.500us | 3 | 3 | 100.00 | |
| chip_sw_flash_scramble | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1783.660s | 18130.844us | 3 | 3 | 100.00 | |
| chip_sw_flash_idle_low_power | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 284.420s | 3430.202us | 3 | 3 | 100.00 | |
| chip_sw_flash_keymgr_seeds | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 1831.910s | 11157.898us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 231.420s | 3014.936us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 4942.010s | 43330.500us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 231.420s | 3014.936us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 231.420s | 3014.936us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 231.420s | 3014.936us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 231.420s | 3014.936us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| chip_sw_flash_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 393.700s | 9678.273us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_clock_freqs | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 732.280s | 5505.481us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_escalation_reset | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 543.780s | 5794.012us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_write_clear | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 543.780s | 5794.012us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc | 6 | 6 | 100.00 | |||
| chip_sw_hmac_enc | 251.380s | 3283.596us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 258.110s | 3340.337us | 3 | 3 | 100.00 | |
| chip_sw_hmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_hmac_enc_idle | 235.380s | 2889.049us | 3 | 3 | 100.00 | |
| chip_sw_hmac_all_configurations | 3 | 3 | 100.00 | |||
| chip_sw_hmac_oneshot | 1334.160s | 7885.202us | 3 | 3 | 100.00 | |
| chip_sw_hmac_multistream_mode | 3 | 3 | 100.00 | |||
| chip_sw_hmac_multistream | 905.330s | 6365.033us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx | 9 | 9 | 100.00 | |||
| chip_sw_i2c_host_tx_rx | 512.370s | 5078.275us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 583.200s | 5450.807us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 555.840s | 5447.064us | 3 | 3 | 100.00 | |
| chip_sw_i2c_device_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_i2c_device_tx_rx | 366.240s | 4102.368us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 6 | 6 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 1831.910s | 11157.898us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 2202.160s | 12771.098us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_kmac | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_kmac | 2130.300s | 11846.893us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_aes | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 1686.130s | 10713.013us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_otbn | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_otbn | 3616.990s | 17468.611us | 3 | 3 | 100.00 | |
| chip_sw_kmac_enc | 9 | 9 | 100.00 | |||
| chip_sw_kmac_mode_cshake | 237.620s | 2906.596us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac | 276.650s | 2933.467us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 295.950s | 3036.856us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_keymgr | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 1831.910s | 11157.898us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_lc | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_kmac_app_rom | 3 | 3 | 100.00 | |||
| chip_sw_kmac_app_rom | 233.270s | 3229.861us | 3 | 3 | 100.00 | |
| chip_sw_kmac_entropy | 3 | 3 | 100.00 | |||
| chip_sw_kmac_entropy | 1947.190s | 10828.846us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_kmac_idle | 214.820s | 2675.149us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 457.690s | 5610.734us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_jtag_access | 15 | 15 | 100.00 | |||
| chip_tap_straps_dev | 1383.360s | 15858.106us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 633.870s | 7110.863us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1442.200s | 10965.183us | 5 | 5 | 100.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 197.090s | 2662.242us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_transitions | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_kmac_req | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_lc_ctrl_key_div | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation_prod | 2118.990s | 13108.142us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 75 | 84 | 89.29 | |||
| chip_sw_flash_ctrl_lc_rw_en | 231.420s | 3014.936us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 4942.010s | 43330.500us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 286.840s | 3623.555us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 760.130s | 7480.224us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 575.390s | 6972.626us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 666.640s | 5714.293us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_keymgr_key_derivation | 1831.910s | 11157.898us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 434.330s | 8348.826us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 825.060s | 8364.455us | 3 | 3 | 100.00 | |
| chip_prim_tl_access | 393.700s | 9678.273us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 473.870s | 7162.236us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 480.570s | 4406.734us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 543.510s | 5104.762us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 526.900s | 4275.521us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 535.650s | 5630.403us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 525.390s | 4438.191us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 499.800s | 4968.209us | 3 | 3 | 100.00 | |
| chip_tap_straps_dev | 1383.360s | 15858.106us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 633.870s | 7110.863us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1442.200s | 10965.183us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 219.100s | 6264.427us | 0 | 3 | 0.00 | |
| chip_lc_scrap | 6 | 6 | 100.00 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 258.280s | 3886.684us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 134.880s | 2851.178us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 125.860s | 3741.715us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 257.630s | 3402.348us | 3 | 3 | 100.00 | |
| chip_lc_test_locked | 2 | 6 | 33.33 | |||
| chip_sw_lc_walkthrough_testunlocks | 2447.020s | 41682.846us | 2 | 3 | 66.67 | |
| chip_rv_dm_lc_disabled | 219.100s | 6264.427us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough | 5 | 15 | 33.33 | |||
| chip_sw_lc_walkthrough_dev | 1138.660s | 10634.317us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 1087.060s | 10768.343us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 801.320s | 8129.574us | 3 | 3 | 100.00 | |
| chip_sw_lc_walkthrough_rma | 541.610s | 6018.758us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 2447.020s | 41682.846us | 2 | 3 | 66.67 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 6 | 9 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 96.150s | 2200.768us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 111.120s | 2303.223us | 3 | 3 | 100.00 | |
| rom_volatile_raw_unlock | 52.402s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 6 | 6 | 100.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 4750.210s | 16919.628us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 4654.810s | 18604.632us | 3 | 3 | 100.00 | |
| chip_sw_otbn_rnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 801.000s | 6502.918us | 3 | 3 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 801.000s | 6502.918us | 3 | 3 | 100.00 | |
| chip_sw_otbn_idle | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 801.000s | 6502.918us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 411.390s | 3977.149us | 3 | 3 | 100.00 | |
| chip_otp_ctrl_init | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_keys | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1783.660s | 18130.844us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 411.390s | 3977.149us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 1831.910s | 11157.898us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 573.380s | 5506.756us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 205.460s | 2612.383us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1783.660s | 18130.844us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 411.390s | 3977.149us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 1831.910s | 11157.898us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 573.380s | 5506.756us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 205.460s | 2612.383us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_program | 15 | 15 | 100.00 | |||
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_sw_otp_ctrl_program_error | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_program_error | 417.040s | 5050.811us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 197.090s | 2662.242us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals | 27 | 30 | 90.00 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 286.840s | 3623.555us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 760.130s | 7480.224us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 575.390s | 6972.626us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 666.640s | 5714.293us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 878.180s | 13808.630us | 15 | 15 | 100.00 | |
| chip_prim_tl_access | 393.700s | 9678.273us | 3 | 3 | 100.00 | |
| chip_sw_otp_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 393.700s | 9678.273us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_dai_lock | 1 | 1 | 100.00 | |||
| chip_sw_otp_ctrl_dai_lock | 1181.620s | 8215.178us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 282.660s | 5695.795us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 1755.510s | 27497.342us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 371.890s | 7438.745us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 468.300s | 8090.776us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 598.940s | 7039.663us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 1395.550s | 25755.306us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 2 | 6 | 33.33 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 833.210s | 13645.346us | 1 | 3 | 33.33 | |
| chip_sw_aon_timer_wdog_bite_reset | 754.880s | 8680.251us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 1340.050s | 13805.457us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_wdog_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_wdog_reset | 464.940s | 5360.441us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 282.660s | 5695.795us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 386.420s | 5492.752us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 950.530s | 11398.971us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 448.480s | 7659.606us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 210.740s | 2612.680us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 340.560s | 5748.090us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 897.750s | 7202.535us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 1603.090s | 14244.033us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2 | 3 | 66.67 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2257.330s | 24104.147us | 2 | 3 | 66.67 | |
| chip_sw_pwrmgr_sleep_disabled | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 241.800s | 3669.783us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_escalation_reset | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| chip_sw_rom_access | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 434.330s | 8348.826us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 434.330s | 8348.826us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 9 | 12 | 75.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1603.090s | 14244.033us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 340.560s | 5748.090us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_wdog_reset | 464.940s | 5360.441us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 460.330s | 5871.249us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sys_reset_info | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 408.760s | 4644.697us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 654.520s | 6065.326us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_req_reset | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 424.200s | 5142.053us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_alert_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1615.020s | 12457.156us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_rst | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 212.890s | 2749.153us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1471.760s | 7924.828us | 3 | 3 | 100.00 | |
| chip_sw_nmi_irq | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 601.990s | 4398.022us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_rnd | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 681.890s | 5192.273us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 261.080s | 3186.694us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 205.460s | 2612.383us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 654.520s | 6065.326us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_double_fault | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 654.520s | 6065.326us | 3 | 3 | 100.00 | |
| chip_jtag_csr_rw | 3 | 3 | 100.00 | |||
| chip_jtag_csr_rw | 1982.430s | 19912.722us | 3 | 3 | 100.00 | |
| chip_jtag_mem_access | 3 | 3 | 100.00 | |||
| chip_jtag_mem_access | 1181.090s | 13458.917us | 3 | 3 | 100.00 | |
| chip_rv_dm_ndm_reset_req | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 408.760s | 4644.697us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 255.750s | 3656.965us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 441.260s | 7433.497us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 5 | 5 | 100.00 | |||
| chip_tap_straps_rma | 633.870s | 7110.863us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | |||
| chip_rv_dm_lc_disabled | 219.100s | 6264.427us | 0 | 3 | 0.00 | |
| chip_sw_plic_all_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 780.310s | 5465.998us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 393.120s | 4465.376us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 521.810s | 4464.835us | 3 | 3 | 100.00 | |
| chip_sw_plic_sw_irq | 3 | 3 | 100.00 | |||
| chip_sw_plic_sw_irq | 284.540s | 3568.940us | 3 | 3 | 100.00 | |
| chip_sw_timer | 3 | 3 | 100.00 | |||
| chip_sw_rv_timer_irq | 225.630s | 2888.907us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_flash_mode | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 3992.900s | 14878.647us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pass_through | 581.800s | 5909.643us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 281.480s | 3318.851us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_tpm | 300.230s | 4126.011us | 3 | 3 | 100.00 | |
| chip_sw_spi_host_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_spi_host_tx_rx | 266.490s | 3404.080us | 3 | 3 | 100.00 | |
| chip_sw_sram_scrambled_access | 6 | 6 | 100.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 573.380s | 5506.756us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 449.160s | 5439.348us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents | 6 | 6 | 100.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 603.050s | 8877.945us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 688.900s | 8914.666us | 3 | 3 | 100.00 | |
| chip_sw_sram_execution | 3 | 3 | 100.00 | |||
| chip_sw_sram_ctrl_execution_main | 825.060s | 8364.455us | 3 | 3 | 100.00 | |
| chip_sw_sram_lc_escalation | 102 | 106 | 96.23 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| chip_sw_data_integrity_escalation | 645.170s | 5636.042us | 6 | 6 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 897.750s | 7202.535us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 1666.470s | 22425.549us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_inputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_inputs | 247.340s | 3515.472us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_outputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_outputs | 329.060s | 3430.066us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_in_irq | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 540.630s | 5455.531us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1666.470s | 22425.549us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_reset | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1666.470s | 22425.549us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3254.810s | 20896.353us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3254.810s | 20896.353us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 3 | 6 | 50.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 519.810s | 6834.386us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.182s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_vbus | 195.550s | 2919.879us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pullup | 233.050s | 3144.488us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_aon_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_aon_pullup | 390.110s | 3957.716us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_setup_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_setuprx | 431.690s | 4065.430us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_config_host | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_config_host | 1320.940s | 7752.083us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pincfg | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pincfg | 6482.400s | 31967.434us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_tx_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_dpi | 2405.270s | 12591.335us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_toggle_restore | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_toggle_restore | 177.070s | 2321.504us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 3 | 3 | 100.00 | |||
| chip_sw_aes_masking_off | 275.780s | 2962.148us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 2 | 3 | 66.67 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 189.970s | 2989.222us | 2 | 3 | 66.67 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 1 | 1 | 100.00 | |||
| chip_sw_coremark | 15307.140s | 71106.188us | 1 | 1 | 100.00 | |
| chip_sw_power_max_load | 3 | 3 | 100.00 | |||
| chip_sw_power_virus | 1469.440s | 6487.296us | 3 | 3 | 100.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 650.760s | 6076.600us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 288.960s | 4287.941us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 292.420s | 5097.382us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 1 | 3 | 33.33 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 105.000s | 2571.440us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 87.320s | 2483.548us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 322.580s | 4098.612us | 1 | 1 | 100.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 54.621s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 356.760s | 3483.223us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_boot_mode | 408.940s | 3381.392us | 3 | 3 | 100.00 | |
| chip_sw_edn_auto_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_auto_mode | 1207.870s | 5925.130us | 3 | 3 | 100.00 | |
| chip_sw_edn_sw_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_sw_mode | 1995.040s | 11087.206us | 3 | 3 | 100.00 | |
| chip_sw_edn_kat | 3 | 3 | 100.00 | |||
| chip_sw_edn_kat | 314.550s | 2254.436us | 3 | 3 | 100.00 | |
| chip_sw_flash_memory_protection | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_mem_protection | 735.540s | 5754.440us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 247.380s | 3487.812us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 260.460s | 3299.734us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 475.180s | 5533.421us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 439.110s | 5448.685us | 3 | 3 | 100.00 | |
| chip_sw_all_resets | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1603.090s | 14244.033us | 3 | 3 | 100.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 650.760s | 6076.600us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 288.960s | 4287.941us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 292.420s | 5097.382us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 555.610s | 6130.686us | 3 | 3 | 100.00 | |
| chip_sw_plic_alerts | 96 | 100 | 96.00 | |||
| chip_sw_all_escalation_resets | 672.110s | 6616.429us | 96 | 100 | 96.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.163s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.163s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 276.120s | 4276.541us | 3 | 3 | 100.00 | |
| chip_sw_uart_watermarks | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 511.590s | 4706.829us | 5 | 5 | 100.00 | |
| chip_sw_usbdev_stream | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_stream | 3933.620s | 19108.706us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 18 | 31 | 58.06 | |||
| chip_sival_flash_info_access | 317.570s | 3776.164us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 29.950s | 10.120us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 8.510s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_ecc_error_vendor_test | 240.020s | 2688.511us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_descrambling | 285.300s | 3276.432us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 322.400s | 3942.433us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 11.640s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 276.810s | 3650.387us | 3 | 3 | 100.00 | |
| ate_bootstrap_flash_erase | 773.160s | 10010.340us | 0 | 3 | 0.00 | |
| ate_bootstrap_one_frame | 9890.260s | 45563.845us | 3 | 3 | 100.00 | |
| ate_bootstrap_disjoint | 10800.171s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) | 90 test runs | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29823386006094904499658374985030647263615846496561739953546243668472561008218 | 308 |
UVM_INFO @ 2521.725912 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 6575942399670061774045657332538081947999416820344999091313820517881014227644 | 308 |
UVM_INFO @ 2781.283200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12423693918211580648453383322081308177514844519448910716029486668830935394458 | 308 |
UVM_INFO @ 2960.819600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13878200361967743192279690806410809113269269146489252729742658536246102504087 | 308 |
UVM_INFO @ 2640.364248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39178095913115848734210294087412048361850739762119135236473194960825992981808 | 308 |
UVM_INFO @ 2858.013600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 71524856307490375940984005715048067459264827856393379741380556294183645228889 | 308 |
UVM_INFO @ 2756.039640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39435440091445128041419575004918777985224260448056204739942455826194627970139 | 308 |
UVM_INFO @ 2575.853266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1180898519967637536557193904847805085995705848317884167254740027640908595296 | 308 |
UVM_INFO @ 2879.115618 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2662147155822851445441564183802323050399315889795896317122603133843091129682 | 308 |
UVM_INFO @ 2901.622768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50999650046515318503734965742472419489834295877758884570594031777014803388561 | 308 |
UVM_INFO @ 3097.613086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 39129772623590432712758647412472951135587442692029488626790948731363555066164 | 308 |
UVM_INFO @ 2607.559248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56830093301356922485334193508499548641361634167230263175528909580638189745008 | 308 |
UVM_INFO @ 3221.706718 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96949792486510801568340825929967800017099663101965198406501913502897114899879 | 308 |
UVM_INFO @ 2703.803330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93614796640562415247610574349131546920403898290194251295265451395845769569086 | 308 |
UVM_INFO @ 2800.642722 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 42231380065785498810640607000775700091370467907669256498389979195115853741097 | 308 |
UVM_INFO @ 3514.222922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 43764472524297796838050969265558155571905132142624759888458005899783085769152 | 308 |
UVM_INFO @ 2819.781199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 82948064185651284575063050852617761607513827578084872547528377775668769417040 | 308 |
UVM_INFO @ 3294.692985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96247438634412469932187866736984264879207184513873138179422973596220452872437 | 308 |
UVM_INFO @ 2471.783875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 53591284191390334550378006737836347744544047409033436139932797193953431708739 | 308 |
UVM_INFO @ 3556.821144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 110198939233476040422871550932568106966907257496793901176811659902668621351857 | 308 |
UVM_INFO @ 2794.050488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 217650777000892918478078051784648134016266316459487915955178713269365780629 | 308 |
UVM_INFO @ 3138.112324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25956915257800968441545185959795017808520500658679555170738858546240540883139 | 308 |
UVM_INFO @ 2679.055832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 108080278970949727637815418539227810013457072134823958188564506643768571204973 | 308 |
UVM_INFO @ 2733.982590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 102726409617087514303864021279640140159436432117173097168827466400593115198503 | 308 |
UVM_INFO @ 3111.465580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 113160432778596580433594495278826080114665056703510384174910737748542342014861 | 308 |
UVM_INFO @ 2358.454608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 74802704406720961118819539902090039942566687760904185471910491515374063106613 | 308 |
UVM_INFO @ 3562.334094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 41229809542557400719318726438918509969313346073506230938493826386550821881273 | 308 |
UVM_INFO @ 3034.563190 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 59709318409309017706302132515776910949454141407046152627255428947075446952578 | 308 |
UVM_INFO @ 2502.475788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25871606970625652196344067676901340901200150127380451604574590901270728411545 | 308 |
UVM_INFO @ 3328.164570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 85285307975978076505946681842708762191624061873578927619267653790428743709938 | 308 |
UVM_INFO @ 2426.412778 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 106986656216472881673517097592721945444677800204814297403143156691033406928509 | 308 |
UVM_INFO @ 2853.947558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 1618495237681692916943172466472000649099145621430795115229913376613005049774 | 308 |
UVM_INFO @ 3087.474876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 38291093803802176067700147254465210524148515185876711736771944262528487703074 | 308 |
UVM_INFO @ 3064.458215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 43632144461230692185807929877490352692789837611309315335817261913066621757311 | 308 |
UVM_INFO @ 3365.943800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16489606420490991917605319813256717337371294189400737879730356366859005901410 | 308 |
UVM_INFO @ 2822.136324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 68056040104778910082285087253784281673213717055726632466326554952549724106136 | 308 |
UVM_INFO @ 2698.099288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 35393371521769996796656529300978923320500773089247476786452857590881108809518 | 308 |
UVM_INFO @ 3219.074010 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25234095236594186804942382491118116929136639649608887396769599557826169653995 | 308 |
UVM_INFO @ 2996.842994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 33635536525349685503262358090836593861045174074892961220713524729103890723639 | 308 |
UVM_INFO @ 3263.833149 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64679653308009634162493207403373261838269303526895132442596653375464654080776 | 308 |
UVM_INFO @ 3411.624977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 38715351457150904625255119979039871480032589257573297816559262676828156325954 | 308 |
UVM_INFO @ 2627.381901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96477316474582860957379734707721628706644965127189068334693772532256580977952 | 308 |
UVM_INFO @ 2948.250644 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 20611803778212958829935716249326465576021026108635274594099962622821198797780 | 308 |
UVM_INFO @ 3463.022412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 18064270211366745515123490987145028014413632617732683177078781381580740034961 | 308 |
UVM_INFO @ 2541.691848 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 86937083908626095191233473653960354160496351034443921076409837281099042080113 | 308 |
UVM_INFO @ 3292.478275 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 32664542938671908955069582938644786150769783514725473719407806467686906116541 | 308 |
UVM_INFO @ 2448.395620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 19863769483371507491638345958733268187911226820735274344877272134756248870818 | 308 |
UVM_INFO @ 3299.383642 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 29052623345625821957973369541571207562117596937205987671978465434072429416638 | 308 |
UVM_INFO @ 2298.679105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3097313141791953745200674171136279849838864321128249007509195604375538610416 | 308 |
UVM_INFO @ 3160.114310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 44959353936182970272899348055745301627481651122657250498962228148470184794535 | 308 |
UVM_INFO @ 2328.784580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 81072617931477099685486285832808612324401444538321508511497681806580839118527 | 308 |
UVM_INFO @ 2389.811490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 99511563989366517371019224924340015336177990494197705409242695076672953411298 | 308 |
UVM_INFO @ 2861.061977 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83564700489178729495246710502256054072781236800350260239864630875646026014341 | 308 |
UVM_INFO @ 3470.790440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93100500381805929831082183848926750662079641474208662259892965319695744774620 | 308 |
UVM_INFO @ 2954.900728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 53960689410720200340462974872187458432184464719886622575675770303483641620217 | 308 |
UVM_INFO @ 3105.756169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 5406936524055707451696753131521595680033516419578374159650124499039271841372 | 308 |
UVM_INFO @ 3264.570375 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 8970953571810080003652075702379131082671074168825665031537656525840786249499 | 308 |
UVM_INFO @ 2747.160024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 48389612923058338539479038843498543782209314337346976268322565073711210433471 | 308 |
UVM_INFO @ 2848.253822 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 40618012924225513941564165326907826235844004548355895934795653775720509134774 | 308 |
UVM_INFO @ 2815.794564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 101634792835436711269445013426464165839139768363304732027629475771445202964112 | 308 |
UVM_INFO @ 2255.678664 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 48579627579711997127384461019579621347932522177498459281373473923585464705036 | 308 |
UVM_INFO @ 3022.488640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 86344993677445101651743408466041735580589459395811874207216662398884307156350 | 308 |
UVM_INFO @ 3208.056807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 52133948107372148646077108364970255303095072483564303971523325320607185267139 | 308 |
UVM_INFO @ 2476.127824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 91940109663258495962098283925564543907175910449858139322318476508015184137168 | 308 |
UVM_INFO @ 2793.708434 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 71140112947668209822191686859799636447156100474364321487790974558553779724629 | 308 |
UVM_INFO @ 2980.459058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 31116411277669954878243947315637372826812861895490591696260132195810743571564 | 308 |
UVM_INFO @ 2964.497344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 73133300971873047997340332423998758112151154530757174335136716468913871039970 | 308 |
UVM_INFO @ 2833.942606 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 45816912600499329319264107005350370018932215772036766899849421956525209345586 | 308 |
UVM_INFO @ 2522.799856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111676459212607868099192201862606841744300200639976012283842138460690751229424 | 308 |
UVM_INFO @ 2916.477880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 115615602440302070363395385669614447732375305049051546453305546765505009479785 | 308 |
UVM_INFO @ 2857.811350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 62507685545688176327010426064654757031439018386702265569757539605055030379109 | 308 |
UVM_INFO @ 2239.583622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13146728484549387335394887790106198651296575529212225466266668556215052805985 | 308 |
UVM_INFO @ 2762.369000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 67586360010528943998326760836857500862896322221293897368361842057987521799845 | 308 |
UVM_INFO @ 3593.610296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 406464657395763627527197336889463132975644213372540197942004516954029833556 | 308 |
UVM_INFO @ 3125.792248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 43131541816141772418077555386691565372474443144739451891385642155624041044257 | 308 |
UVM_INFO @ 3160.675661 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 96133989892064729037875932146686667215111284042071327000066572310692999667396 | 308 |
UVM_INFO @ 2651.139249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 103063666473330644385426753530036739240805450519737531700479329149657425642109 | 308 |
UVM_INFO @ 2190.044831 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3720534155437921708769574654169977042975948037552954548033927524344457437542 | 308 |
UVM_INFO @ 3147.460196 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 84265115661547514983599907171114266995356626808983932563097847468398513714283 | 308 |
UVM_INFO @ 3657.890432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 79766008110139773211269532905574632960971022730405775116180434846261643364053 | 308 |
UVM_INFO @ 2731.316312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111254078208260570703722669169177516796240907775434503408608221247287860845138 | 308 |
UVM_INFO @ 2327.435424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 103559385920415142651805423269466219924408236140391542645114946533458691389237 | 308 |
UVM_INFO @ 2994.974080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 79205109770180694909757588771132375584986776953869484625776525522473161591437 | 308 |
UVM_INFO @ 2589.192272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 94917491253508611314732336494750876616998712558893205910427079184067939896454 | 308 |
UVM_INFO @ 2734.669779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 86271833604625415914848122638584170530656236949769251527668530166088186302139 | 308 |
UVM_INFO @ 2921.016481 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 105223838111621500728166688034248471790284971224939390418831989923904734526088 | 308 |
UVM_INFO @ 2544.908334 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83489688858650651696734957105436536834223597842854767681608542809853334212656 | 308 |
UVM_INFO @ 2735.383061 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13198516978986962979711425890113198942790788794852043346594245422847809597725 | 308 |
UVM_INFO @ 3527.685000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 95130371097211992366174191386497750217114709519995437446973101182306141849504 | 308 |
UVM_INFO @ 2836.586012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 80724600684984096901840934827797973870519121756226113618597272100746937973494 | 308 |
UVM_INFO @ 3079.014012 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 42 test runs | |||
| chip_sw_pwrmgr_sleep_wake_5_bug | 35378683183310678843586522372594288866976402854846605653139340836464123295320 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 44187728856895246065296636480760404361175551612275300583230983369042754421971 | None |
---- STDERR ----
Another command (pid=280330) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283556) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 100715141420080468091880810281178069211591537790045684505542651818084481815645 | None |
---- STDERR ----
Another command (pid=367228) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=359428) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 20340922064083425082901795807535445542229055281941080920965726454864398029646 | None |
Another command (pid=390468) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=338458) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=388634) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 775122385017503271953390504863258811620131686585739360745947158356464930844 | None |
Another command (pid=338458) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=388634) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=376183) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 40685448599939816683699496117577297610009719412654477297727825225288750691483 | None |
Another command (pid=409079) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=413560) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=394486) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 35522638501570692279529238054411689592460202937361041724180837763445378375095 | None |
Another command (pid=283295) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=285837) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=287103) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 60748473070007659948219941533469935891371970237393289762370948699764973420762 | None |
Another command (pid=352492) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=298242) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=340104) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 83087784089574511158716171435687208850582707231238886626889111551976462288499 | None |
Another command (pid=380080) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=416781) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=415067) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 5461156165334618821464020602516272534863790549035019555668518666312557162844 | None |
---- STDERR ----
Another command (pid=360939) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=359232) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 57793615773978815578192998014316681971882529567999643594854021869762441945859 | None |
Another command (pid=351761) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=375900) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=330275) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 72595194347953712040531009151990083758568702459560730693213996094486240435656 | None |
---- STDERR ----
Another command (pid=281819) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 36085782481737619280323670920522302979679685963575056932923663648004072730481 | None |
Another command (pid=328146) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=294777) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=341025) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 91053584111428965278897528168888240850271089122419777966324134918468036335071 | None |
Another command (pid=390468) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=338458) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=388634) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 85383491856137903525336737205599125854768688460884215200862182573559665457751 | None |
Another command (pid=392031) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=380036) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=390468) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 106043503503748291925603601286260586718703022918078521947087981854953490524097 | None |
Another command (pid=354534) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=355008) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=331762) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 31816265730578578736078423392247871156113833018068229406497476308344722639747 | None |
Another command (pid=287290) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=280943) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=280473) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 88269505275888020365455350336704180144003031635916576774356898149899607025257 | None |
Another command (pid=298832) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=296063) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=315550) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 30236766793239147230849445634433644343607670094082977409245863822700340959476 | None |
Another command (pid=302563) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=320772) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=321080) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 24046144354428032336168104486833476899817627695748265322367373765483952296369 | None |
---- STDERR ----
Another command (pid=293277) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=305140) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 36231437438304485838104270554419220162716492831327863435960968004831524675189 | None |
Another command (pid=320214) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=289360) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=327790) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 72931374910544287957235186594566345174545563231127123334725347291649773963619 | None |
Another command (pid=283556) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283766) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283295) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 49929014105825788352687078661431971202421913400462769763532712145143277915696 | None |
Another command (pid=287006) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=289109) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283912) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 88661114097739265011076120292084705752333886195351494197930717975024612179836 | None |
---- STDERR ----
Another command (pid=280330) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283556) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 8386303720324162509591327205884161578268893427238942488960291231564971589252 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 58150923868610412967933859025511079106897609191161931065827815006766175454187 | None |
Another command (pid=281384) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=284185) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=287006) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 46961370591257076758822240422144063378672524865730810930769465446632881588739 | None |
Another command (pid=338458) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=395406) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=388634) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 66082488694963443532080522554155394529304532503963485023490552341276477575765 | None |
Another command (pid=407850) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=406030) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=406732) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 12862706779163511266932272973654217985439415922574276505371934504821706498869 | None |
---- STDERR ----
Another command (pid=404462) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=396167) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 68150187408876826556797229252590752639379366062245337926129799750869955276008 | None |
---- STDERR ----
Another command (pid=404462) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=407601) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 98478213407691916720373678948432755132805444366531368746592281466544463348609 | None |
Another command (pid=283347) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=287006) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=289109) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 19752170739712995025427626497505100978043395741249824294173247116049226767807 | None |
Another command (pid=288207) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=291210) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=280524) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 82469984263109410989690601288525024188880362879949709156553847171327141628749 | None |
---- STDERR ----
Another command (pid=280330) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283556) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 80523308356604455174495620070521539303125510082003743668355907889524268443660 | None |
---- STDERR ----
Another command (pid=460473) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 93405191343951314686975928735834613695460819586115273525775012523094011991672 | None |
Another command (pid=280696) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=280731) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=290117) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 68291871547865354245248129793726087052825569142628609325326800198796949062704 | None |
---- STDERR ----
Another command (pid=407601) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 28417337923928693586940216132766165145734809527310746904420491351299757961997 | None |
Another command (pid=380080) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=416781) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=415067) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 84304377386472231931056761517575650727516511136816577373428512806598733618963 | None |
Another command (pid=428685) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=430218) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=431861) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 30440699025990547533333850480966365015828604012985208218028553129903509214424 | None |
Another command (pid=454040) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=460536) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=459648) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 85898974317328195019989458733622628553156490783833748754794213763157547009950 | None |
Another command (pid=291210) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=284637) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=283820) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 80703709521060031799574360317855979724416409215765874130129937057857090686572 | None |
---- STDERR ----
Another command (pid=284185) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=287006) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 92295569295309539242804479729789392884207097449013275636110495587764651836980 | None |
---- STDERR ----
Another command (pid=283295) is running. Waiting for it to complete on the server (server_pid=280341)...
Another command (pid=285837) is running. Waiting for it to complete on the server (server_pid=280341)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 41 test runs | |||
| chip_tl_errors | 66042126948959449965710690863641650672270361372612551804077788660971456724209 | 217 |
TL item was: req: (cip_tl_seq_item@35582) { a_addr: 'h1040c a_data: 'hf5070afc a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h18db9 d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2226.069425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 45415129859325904929314071281116825767579247068660884542769058271394071487707 | 217 |
TL item was: req: (cip_tl_seq_item@35318) { a_addr: 'h10724 a_data: 'h7f87ff3c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h18dcd d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2617.405004 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 90151985981958394594610309536002302948178846491865909520833745485593907619319 | 224 |
TL item was: req: (cip_tl_seq_item@31888) { a_addr: 'h10424 a_data: 'h1b086a96 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h18194 d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2548.260876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 61740388796414803868897558137574744112769578639055120436826018534431972807556 | 217 |
TL item was: req: (cip_tl_seq_item@32244) { a_addr: 'h10738 a_data: 'ha115de9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h1b167 d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1980.817658 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 69105402604207256622539734193424969043754620235415477120657545145750538002653 | 242 |
TL item was: req: (cip_tl_seq_item@211616) { a_addr: 'h1052c a_data: 'h444b1ef6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1922f d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 5518.657875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 48337626724458587329145160476716583362906534270845051615238148354385084556350 | 217 |
TL item was: req: (cip_tl_seq_item@31844) { a_addr: 'h10518 a_data: 'hc30d1fab a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1a286 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2262.699770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 19361364282744920745554287170846354664096375297293641352885805682682449227629 | 224 |
TL item was: req: (cip_tl_seq_item@31526) { a_addr: 'h104b8 a_data: 'hfee38c37 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h36 a_opcode: 'h4 a_user: 'h18de4 d_param: 'h0 d_source: 'h36 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2271.367459 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 103252878544141647221968998975200684904905896142797427832110929939884136589063 | 217 |
TL item was: req: (cip_tl_seq_item@34198) { a_addr: 'h10538 a_data: 'hc2a753bb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h1ba0d d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2397.399188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 63777683759155157909934700760143525758305205969823405283336623947669929015480 | 224 |
TL item was: req: (cip_tl_seq_item@32166) { a_addr: 'h10618 a_data: 'h1fd381f7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h1ae8a d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1764.933786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 91151971829199952652417850607664535628158493252745344907348666572780636457589 | 217 |
TL item was: req: (cip_tl_seq_item@32768) { a_addr: 'h107f8 a_data: 'h454372a0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h1a93d d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2996.507421 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 115063619328630034977452226859961198000469714687516613752517118768524881567581 | 217 |
TL item was: req: (cip_tl_seq_item@31576) { a_addr: 'h10710 a_data: 'h7c409 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2f a_opcode: 'h4 a_user: 'h1bd13 d_param: 'h0 d_source: 'h2f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1894.960176 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 80008286272016777250957853796486554430421879510102117443708581670602567907967 | 224 |
TL item was: req: (cip_tl_seq_item@31570) { a_addr: 'h105d8 a_data: 'h7124c3c8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h30 a_opcode: 'h4 a_user: 'h1ba98 d_param: 'h0 d_source: 'h30 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2655.063725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 2116132846570836468567543780095797924024114746431597299188450500002151510664 | 217 |
TL item was: req: (cip_tl_seq_item@33650) { a_addr: 'h107c4 a_data: 'hb54071a5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h18d08 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2686.929250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 53930439739554526075516933519888717285788246782412169008153744341019773675071 | 224 |
TL item was: req: (cip_tl_seq_item@31722) { a_addr: 'h10384 a_data: 'h23011a0f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h4 a_user: 'h1b6dc d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2193.038060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 87668685790353575804346325246796437517407708454073671399260974928515607177351 | 217 |
TL item was: req: (cip_tl_seq_item@39012) { a_addr: 'h106e4 a_data: 'h467c4d6d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h192ad d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2639.917183 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 3913891523419200828230291817388978608477052066429622025531968062748312212872 | 224 |
TL item was: req: (cip_tl_seq_item@32158) { a_addr: 'h10558 a_data: 'hba758295 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3f a_opcode: 'h4 a_user: 'h18a7a d_param: 'h0 d_source: 'h3f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2510.379720 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 73513455700781366526618987328974056710186320688715550331841991402355462735715 | 242 |
TL item was: req: (cip_tl_seq_item@212616) { a_addr: 'h104cc a_data: 'h9910c0e1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h195bf d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 5994.603160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 160351134900108738171653067486129834126870582037775662825694421407492718073 | 217 |
TL item was: req: (cip_tl_seq_item@32814) { a_addr: 'h10354 a_data: 'hf5ecd0a1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h18a33 d_param: 'h0 d_source: 'h4 d_data: 'h13 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd7d a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2249.703970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 52324700564181589623623558324368417664898979377848722237211630923758992272064 | 224 |
TL item was: req: (cip_tl_seq_item@31682) { a_addr: 'h1047c a_data: 'h3090292c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h5 a_opcode: 'h4 a_user: 'h19904 d_param: 'h0 d_source: 'h5 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2287.892411 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 111726483621043082025398726583784677373664862641850830655060432788122237223219 | 217 |
TL item was: req: (cip_tl_seq_item@32090) { a_addr: 'h104e0 a_data: 'he25fd02c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3 a_opcode: 'h4 a_user: 'h19508 d_param: 'h0 d_source: 'h3 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2160.205692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 12705956757665107025252857272264647898311475113261211022400891568213831134295 | 218 |
TL item was: req: (cip_tl_seq_item@142076) { a_addr: 'h10614 a_data: 'he9d414b9 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h1b6de d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2691.687726 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 11671728957440514301581698366878726587027594453471438772167557313879869235111 | 242 |
TL item was: req: (cip_tl_seq_item@214802) { a_addr: 'h10680 a_data: 'h6ce79712 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h1ae06 d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6874.390572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 96134141701078988189353557058698256850012005851673511760937184475788607313230 | 217 |
TL item was: req: (cip_tl_seq_item@34072) { a_addr: 'h10658 a_data: 'h8a3a223b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h18613 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1768.452024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 103951765998861407076493612046070561384082799355364508363883447387271101134932 | 224 |
TL item was: req: (cip_tl_seq_item@31642) { a_addr: 'h1047c a_data: 'h34f31974 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h7 a_opcode: 'h4 a_user: 'h1992a d_param: 'h0 d_source: 'h7 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2275.576780 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 23503008838992661717596060646085329311086309785074703869891773765626665347744 | 217 |
TL item was: req: (cip_tl_seq_item@37720) { a_addr: 'h106fc a_data: 'h222b5967 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1a2cd d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2411.009096 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 10166226295301214440565187671125857112865611432815077785068757551203884740729 | 217 |
TL item was: req: (cip_tl_seq_item@38140) { a_addr: 'h10574 a_data: 'ha11c325b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h18aa9 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1823.598940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 70329830927169728663428367671410557108897051530954662134507806270488158080110 | 224 |
TL item was: req: (cip_tl_seq_item@31940) { a_addr: 'h10338 a_data: 'hb13ec714 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h10 a_opcode: 'h4 a_user: 'h1a257 d_param: 'h0 d_source: 'h10 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2236.175024 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 9932595865245183194895939812391513255703599611645016160906313189655240923851 | 217 |
TL item was: req: (cip_tl_seq_item@36816) { a_addr: 'h105b8 a_data: 'hcd2e6568 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h33 a_opcode: 'h4 a_user: 'h18adb d_param: 'h0 d_source: 'h33 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2216.103081 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 10192078136107209221480729528863744248488341433363192262672533644391976246897 | 217 |
TL item was: req: (cip_tl_seq_item@32466) { a_addr: 'h1071c a_data: 'h3f2dbcdd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h21 a_opcode: 'h4 a_user: 'h1a535 d_param: 'h0 d_source: 'h21 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2270.217672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 58422165615957992903247569213843142070713384843901703830747194681254942573952 | 224 |
TL item was: req: (cip_tl_seq_item@31556) { a_addr: 'h1063c a_data: 'h897887b8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h31 a_opcode: 'h4 a_user: 'h1baec d_param: 'h0 d_source: 'h31 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2725.729124 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 37835725594278367233556647521588982775653055606506135379008179227706550340325 | 217 |
TL item was: req: (cip_tl_seq_item@33732) { a_addr: 'h10374 a_data: 'h85561eed a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h192fd d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1791.323866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 79753248882313420786501122193877911689569551320932189109132314577180317408295 | 224 |
TL item was: req: (cip_tl_seq_item@31978) { a_addr: 'h106b4 a_data: 'haa1334d4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3a a_opcode: 'h4 a_user: 'h19ec5 d_param: 'h0 d_source: 'h3a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2192.240294 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 53172746117242668497492197559745111888452732570133252244885688812611490100450 | 217 |
TL item was: req: (cip_tl_seq_item@32312) { a_addr: 'h10340 a_data: 'h74cdc474 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1a243 d_param: 'h0 d_source: 'h4 d_data: 'hc55513 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd33 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1958.655976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 112087189646681005867938277178181963452179324236663933395624764465722706536585 | 217 |
TL item was: req: (cip_tl_seq_item@43088) { a_addr: 'h107ec a_data: 'h9d8cadb3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h18157 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2650.227065 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 98367718151110109250715230441264165043207632989313398110543583775738157260175 | 217 |
TL item was: req: (cip_tl_seq_item@31568) { a_addr: 'h10580 a_data: 'haf9c0b62 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hd a_opcode: 'h4 a_user: 'h1a243 d_param: 'h0 d_source: 'hd d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1773.623400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 67363296258343698153409901867757797364362003542896369149174268317736699340971 | 217 |
TL item was: req: (cip_tl_seq_item@32242) { a_addr: 'h10548 a_data: 'hcf44f3ce a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1aed0 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2589.361322 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 99429930556696247829739683881125484754403245744786160221573172799898944678772 | 217 |
TL item was: req: (cip_tl_seq_item@32796) { a_addr: 'h106b8 a_data: 'h67848670 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h186cd d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2830.968494 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 47967781098664318830589399088585381711949327605290484275977784461061813490008 | 217 |
TL item was: req: (cip_tl_seq_item@35000) { a_addr: 'h10440 a_data: 'ha8aad94e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1bd7f d_param: 'h0 d_source: 'h9 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2431.949973 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 20663711862243549546755496120784697851521994548569762663692732876528297647037 | 217 |
TL item was: req: (cip_tl_seq_item@33120) { a_addr: 'h104fc a_data: 'h617c2b8c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1a9da d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2183.794590 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 85718075453094655841476870474813466000082799521755993571666755956332362605905 | 217 |
TL item was: req: (cip_tl_seq_item@31496) { a_addr: 'h10698 a_data: 'h6cba265e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h19e72 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1832.987564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 110201201958389900597428310245023772200830121595958673491216075434322063452579 | 217 |
TL item was: req: (cip_tl_seq_item@37914) { a_addr: 'h10618 a_data: 'h64b58be6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1aec4 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2412.491792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 12 test runs | |||
| chip_sw_rv_timer_systick_test | 72920316990133062981698385342095168602608923794650122952246062687805459501348 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 37400628884842297751901717276928408644714455583128761517281918826326110578130 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 84454494144211819644194238860513036471340245760884281917026196535741265832419 | None | ||
| ate_bootstrap_disjoint | 56937873237887768299464618499129126254092103454121373456502715092130568794656 | None | ||
| chip_sw_rv_timer_systick_test | 28463891924105766844408671574576091569640393303236089464325394926903561465023 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 14767537030818485389968482988270514290246147059668341166023691235645769352785 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 51403287153702348547932931944611659552420216985626700378603387667844593217040 | None | ||
| ate_bootstrap_disjoint | 31950014025391623027143460339278008404129161885682680280615979525231284861547 | None | ||
| chip_sw_rv_timer_systick_test | 15193361405731520148395668676602607646589061929716243032698228543759235737742 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 75993443797156394503055831635208761931188639414095155160004841720893857230259 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 70008318581523732896130385837578353007771468232133629791282059386453757354140 | None | ||
| ate_bootstrap_disjoint | 60486785497969058451848570709829597414146797540216566448035522162153883617089 | None | ||
| Offending '(rstreqs[*] && (reset_cause == HwReq))' | 10 test runs | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 27475656908715843745451134438635677978991071016691901866469572910389674931712 | 315 |
UVM_ERROR @ 5748.090000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5748.090000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 80182453184385587186563323324751585102465874014963405017895188691748729005196 | 315 |
UVM_ERROR @ 5692.618000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5692.618000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 39237477719534110082417773493419132690991449974005353398359320104723260394137 | 314 |
UVM_ERROR @ 6401.770000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6401.770000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 105887291542691059752365786375832760302229054788371615740284424063773037329118 | 325 |
UVM_ERROR @ 6857.802500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6857.802500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 108417253017351163967194180023798376441139134454109963104133145307566732169573 | 341 |
UVM_ERROR @ 10417.126000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 10417.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 84263513228976805096153519545630354258661890320227513426743147850585931141089 | 319 |
UVM_ERROR @ 7324.745000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7324.745000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 95390820574153730251862222740521116819061749413103989974428240124070329139108 | 315 |
UVM_ERROR @ 5608.655000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5608.655000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 40502012482348206512305589122342512917471306151737768339479881193001325275002 | 314 |
UVM_ERROR @ 5764.898000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5764.898000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 53624149983945888541099111871750376645989759863276209366676544743978484794147 | 325 |
UVM_ERROR @ 7704.248000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7704.248000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 107176540190716339677234703911231353808068167109923466770514999485617222654685 | 319 |
UVM_ERROR @ 7967.480500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7967.480500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 9 test runs | |||
| chip_sw_lc_walkthrough_dev | 78598373021479364373621885979190952213308451308683966454965221409877633565350 | 369 |
UVM_INFO @ 9035.198688 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 20844634990485451954876389957873842861676182908985289815197590512129397594643 | 369 |
UVM_INFO @ 10768.342604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 103108685520761678132652324280263602364619220862913756823295326097904590597165 | 341 |
UVM_INFO @ 5559.019786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 23670269285592180761830835721334657900480299955745597664089195077392492404530 | 369 |
UVM_INFO @ 10634.316960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 52177622872515597062320825121910132188062425404164326704370515202052640985536 | 369 |
UVM_INFO @ 12172.370265 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 53055281368192626498832673502705709253070071667878934766440246284337192539746 | 341 |
UVM_INFO @ 6018.757763 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 6582047948693381703204884925936779380008052850647713026172726946098127389433 | 369 |
UVM_INFO @ 11832.843930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 109879924523233211038078434227524878347103855749311252322008785423025500662195 | 369 |
UVM_INFO @ 8509.056064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 17134276301400697321535838617059044928062655619487682038625018446831611467410 | 341 |
UVM_INFO @ 5371.106172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[NOA] Null object access | 8 test runs | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 24220042263778126327708270507531684651330291112425335738381367610491837173017 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 78257356666205636721877078571682340033935680243149351187786836317737833487703 | 352 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_dev | 56893901629697272709929395780001306179888846728194367088375916368702667700075 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_rma | 13480954638387091758479042408357764961564169982711256073610132923762664340179 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 102838775433787859802364758991124588972113834992633005485834243414989260409956 | 305 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_dev | 21035687540218201805695918612305715331293045171681707757421516125329505967988 | 305 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 56787747891587598807236868394197748444581875117776230192754635554157404566711 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 101759788064031146933043548636685495880238761472898381365123648779725353330807 | 332 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 6 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 28667261391912033773393546251493574505234555276099005426254839968699823212408 | 368 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 6240006489036473359434926413007184106187308137553107562112124867037215446504 | 365 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 81287547641397195391212178850444479426691244293033645025281035976631061128014 | 366 |
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 99483147402869676704257730386811906444185849313738529839425230879888706330560 | 326 |
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 46480245675451121024931415798587783030301688761958709798231371607568835575293 | 328 |
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 92841718572425261598842279243319266127843378406756304314676005982320267325806 | 325 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' | 5 test runs | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 94043485968474164446120179862019628658321534259388222154626634612814802312589 | 313 |
UVM_ERROR @ 3383.189438 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3383.189438 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 74832781118176039546588151726288263536021351047838995066802661040906616874717 | 315 |
UVM_ERROR @ 4367.551986 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4367.551986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 103249689878417783461789512530837329197738442621544090369525447822164637711016 | 313 |
UVM_ERROR @ 3653.393866 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3653.393866 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 75233626300416615868171529694896129577901210091830766730385651801113911460052 | 313 |
UVM_ERROR @ 2612.679564 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2612.679564 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 35824972781709499984435186616219678328677790405917169741971187549950363307175 | 357 |
UVM_ERROR @ 11398.971257 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 11398.971257 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 4 test runs | |||
| chip_sw_pwrmgr_full_aon_reset | 81955161626502722987976854464182569240160497913936637138370454605928090058317 | 320 |
UVM_ERROR @ 4792.318844 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 4792.318844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 92487919973489080152956241563278179106858173041458891184734671925576535119069 | 320 |
UVM_ERROR @ 5695.795058 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5695.795058 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_b2b_sleep_reset_req | 99774785832185068478601148217608370689102944221322664447200584389644513802438 | 412 |
UVM_ERROR @ 32079.285000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 32079.285000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 4414051438336747329311447278643404534242510165513700954796399259556029376504 | 316 |
UVM_ERROR @ 6790.997386 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6790.997386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path | 3 test runs | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 108616925337875386141177693105712448851421212914558103178101630962020972005473 | 301 |
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 103264016453823735467883074576963993625139743598893535328520105913621578818575 | 301 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 72739258035517067834347356162024541718858233264093079259387121362493926653914 | 301 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_flash_ctrl_lc_rw_en | 70390248658619509963411793662287916978316153573959215063491594574954535837223 | 309 |
UVM_INFO @ 2781.042715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 26650900775604210186939244304970878781402117544927102178162714832631456979156 | 309 |
UVM_INFO @ 2952.318472 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 36680104171648629028522398581898169943290618749791742007587746050914387664126 | 309 |
UVM_INFO @ 3014.936080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * | 3 test runs | |||
| chip_sw_otp_ctrl_lc_signals_rma | 92999426276406178468341790893933936672282945431937315113920051679696896971473 | 342 |
UVM_INFO @ 6518.244849 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 66669134426190800648661099544095746235706341453403123015976526663402529802359 | 342 |
UVM_INFO @ 6848.045290 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 89830356705769786951240964465575880085057942967715600677748679325889031085042 | 342 |
UVM_INFO @ 5714.293458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 3 test runs | |||
| chip_sw_otp_ctrl_escalation | 88888027145979723480862392454575111852313528007553638702530213515549438711708 | 316 |
UVM_ERROR @ 3299.733504 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3299.733504 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 541610273348071389227574301542547056996993304959945897495352113697951022779 | 312 |
UVM_ERROR @ 3413.960496 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3413.960496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 79698362157874770577381633928171231656288002037434225677623278611994577450384 | 312 |
UVM_ERROR @ 3125.518484 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3125.518484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_clkmgr_jitter_frequency | 47398349314090627978946594536736573848677235361272740732870785950253190738878 | 343 |
UVM_INFO @ 3053.704133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 13527436805596770028254039114515211861503061402041143131981311642487135203403 | 343 |
UVM_INFO @ 3483.223356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 31815717267371359417212890628408145364250624917893911035769957405363137329894 | 343 |
UVM_INFO @ 3573.444499 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 3 test runs | |||
| chip_rv_dm_lc_disabled | 12903828731055227168508223403460697364542726323988433794163675549402960720568 | 215 |
UVM_INFO @ 2568.901797 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 104890059568291423420011448514315529333776688374603678276518950693254571786040 | 225 |
UVM_INFO @ 2800.154576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 96141064516755194635979286904941935423814427328548321194112627963379822409250 | 245 |
UVM_INFO @ 6264.427303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_idle_load | 51506182731857454450521460369153870659931117354842817014501748711065093534796 | 312 |
UVM_INFO @ 3009.312000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 72264920224885555850675030891180913338223904886771955275808464797159549259799 | 312 |
UVM_INFO @ 3983.015000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 92729910259275769680793875750767311826414142706854816117206968672342845813146 | 312 |
UVM_INFO @ 3525.752500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_sleep_load | 111192755178015333458361661387524032775695652716628617619960766932072716574059 | 319 |
UVM_INFO @ 2853.008000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 878238093630333877024661323819356604878357107655546160876400365171394294245 | 318 |
UVM_INFO @ 3235.376000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 83405028649772281802061455227684536794327274083297781473310775194996428227808 | 318 |
UVM_INFO @ 3593.420000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * | 3 test runs | |||
| chip_sw_ast_clk_rst_inputs | 50531153640717024473382787740413171948241904593235223329650535526129103333813 | 327 |
UVM_INFO @ 13271.468947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 56283138902157410394078577595067292370649756345879554843970959104023988687119 | 327 |
UVM_INFO @ 11859.565364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 30537819660026352838018727644624663525923624730619135366169502121137337390378 | 327 |
UVM_INFO @ 11405.641761 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) | 3 test runs | |||
| ate_bootstrap_flash_erase | 74678655261693504611073263083862467530562371272897125697069840092648393259166 | 272 |
UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 36549584891408676716738392458634785861713079372963404384956370952892620748143 | 272 |
UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 1723547899338651012938007380717159022018368350289128347208059603832121994107 | 272 |
UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 3 test runs | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 86072182115038227489850527655129510950520987936848993933899192558521172997859 | 327 |
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 61151394237242154127871758831616517123549924507841836325069510796143684990477 | 328 |
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 52886576904143545819190341768312131809126161778276812391550114121902042377500 | 327 |
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 3 test runs | |||
| rom_e2e_keymgr_init_rom_ext_no_meas | 16111512965315290930555466073218521511831232449572078564722637477525257455887 | 319 |
UVM_INFO @ 15908.105052 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 51292587348030539058582030117399985175177712150824897243582232310904811549754 | 319 |
UVM_INFO @ 16276.947816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_keymgr_init_rom_ext_no_meas | 113196165374052867149400489300908356530428337377759550040048285957708238103264 | 319 |
UVM_INFO @ 16384.020604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '$stable(key_data_i)' | 3 test runs | |||
| rom_keymgr_functest | 10907980670877479542395654343979181637792000027822537540475258635898820189657 | 327 |
UVM_ERROR @ 4128.375263 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4128.375263 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 18354385769811274445157579120324694632283083375760206061676516247301877732180 | 327 |
UVM_ERROR @ 4123.776169 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4123.776169 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 19747109893575918190859081206365461695176620860801097912150054643525649004823 | 327 |
UVM_ERROR @ 4289.129312 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4289.129312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *! | 2 test runs | |||
| chip_sw_alert_test | 58683720563779344662967541436654376254377795294683063057327670003676824652258 | 307 |
UVM_INFO @ 3668.810646 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_test | 69772974158073238035599712130760885031454677711216548626201852227783304503496 | 307 |
UVM_INFO @ 2835.359323 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(reset_cause == HwReq)' | 2 test runs | |||
| chip_sw_sensor_ctrl_alert | 2293084796961380996903472628124704818506801174267103497299312482054378087890 | 331 |
UVM_ERROR @ 3986.881896 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 3986.881896 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sensor_ctrl_alert | 21933527775670715899744801782552182730894069799847044213519326406843295748148 | 316 |
UVM_ERROR @ 3515.912920 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 3515.912920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 56544904134253050628259893449988773752078962061020464495179155382576550344821 | 364 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 99099304262385877989415124474855650877072409041594836809931992307073028722360 | 325 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 29466169370369666801198716940486301611560272541363471556496993982310646825972 | 368 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 49036970017473666567421819302759909036737025345811507360557787708967096872132 | 328 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 2 test runs | |||
| chip_sw_spi_device_pass_through_collision | 22001453215796325920275479389445967413349744318544200492107333833642880677254 | 320 |
UVM_INFO @ 3318.850868 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 18625755134596337793397527509761375396733660870918670681925331819451341661461 | 320 |
UVM_INFO @ 3461.311816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:912) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. | 2 test runs | |||
| chip_sw_all_escalation_resets | 88207366938865349100746792102619182748551177146363615213039680915640593256449 | 316 |
UVM_INFO @ 2612.320084 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 86764302338181283650220833805067739507358803689004633737667556469964955405199 | 316 |
UVM_INFO @ 2805.307240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * | 2 test runs | |||
| chip_sw_all_escalation_resets | 72882622717297737905583162611974078209000559060069516489803373829248508174374 | 317 |
UVM_INFO @ 3415.105008 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 69599750815110249003860755894348300511522949066525666730760789092669202379356 | 317 |
UVM_INFO @ 3302.175372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch | 1 test run | |||
| chip_sw_spi_device_pass_through_collision | 72694070318097168688156893161445893616523733886468300521993398262422329621934 | 322 |
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_otp_ctrl_rot_auth_config | 97378332483239488366832901475137325417781664526332331250510992022358290091235 | 282 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 68460494494516287867470194137533412899909613644693612861237455493525888665984 | 325 |
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 7985472256958382322014631623333520420548641470941466461345095024778658979046 | 327 |
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_walkthrough_testunlocks | 4616423216511787968133200542271050865065627073832754017291841835825287695300 | 419 |
UVM_INFO @ 41682.846273 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*] | 1 test run | |||
| chip_sw_sleep_pin_mio_dio_val | 14118217067375666784518088987769625379035373113394330578449978712723829495971 | 451 |
UVM_INFO @ 2980.325000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 25142520254581754612305074008687844190459207451926086869169658285969277438087 | 307 |
UVM_INFO @ 3037.908420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. | 1 test run | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 82346265795327534316447356787661469626006497070802051623688051707413129728601 | 331 |
UVM_INFO @ 2989.221774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 1 test run | |||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 83143004962472496577229850935435552431601591344371784235378247553663914640178 | 319 |
UVM_INFO @ 18004.221560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|