Simulation Results: clkmgr

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.36 %
  • code
  • 98.94 %
  • assert
  • 96.33 %
  • func
  • 87.82 %
  • line
  • 99.36 %
  • branch
  • 99.21 %
  • cond
  • 96.14 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.26%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.750s 353.297us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.210s 18.837us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 6.980s 1059.555us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 1.930s 196.232us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.160s 39.741us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
clkmgr_csr_aliasing 1.930s 196.232us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.430s 150.788us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 2.670s 413.357us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 2.230s 262.933us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.380s 107.555us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.750s 353.297us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 13.960s 2476.335us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 13.480s 2302.668us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 13.960s 2476.335us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 97.730s 12298.066us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.460s 127.855us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 6.240s 1066.177us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 6.240s 1066.177us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.210s 18.837us 5 5 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
clkmgr_csr_aliasing 1.930s 196.232us 5 5 100.00
clkmgr_same_csr_outstanding 2.060s 115.328us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.210s 18.837us 5 5 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
clkmgr_csr_aliasing 1.930s 196.232us 5 5 100.00
clkmgr_same_csr_outstanding 2.060s 115.328us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 11 25 44.00
clkmgr_sec_cm 3.370s 547.412us 2 5 40.00
clkmgr_tl_intg_err 51.030s 10020.363us 9 20 45.00
shadow_reg_update_error 10 20 50.00
clkmgr_shadow_reg_errors 981.910s 200000.000us 10 20 50.00
shadow_reg_read_clear_staged_value 10 20 50.00
clkmgr_shadow_reg_errors 981.910s 200000.000us 10 20 50.00
shadow_reg_storage_error 10 20 50.00
clkmgr_shadow_reg_errors 981.910s 200000.000us 10 20 50.00
shadowed_reset_glitch 10 20 50.00
clkmgr_shadow_reg_errors 981.910s 200000.000us 10 20 50.00
shadow_reg_update_error_with_csr_rw 8 20 40.00
clkmgr_shadow_reg_errors_with_csr_rw 1030.330s 200000.000us 8 20 40.00
sec_cm_bus_integrity 9 20 45.00
clkmgr_tl_intg_err 51.030s 10020.363us 9 20 45.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 13.960s 2476.335us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 13.480s 2302.668us 50 50 100.00
sec_cm_meas_config_shadow 10 20 50.00
clkmgr_shadow_reg_errors 981.910s 200000.000us 10 20 50.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 2.230s 285.705us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.850s 186.452us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.550s 243.099us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 48 50 96.00
clkmgr_clk_handshake_intersig_mubi 1.690s 181.186us 48 50 96.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.480s 72.029us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
sec_cm_idle_ctr_redun 2 5 40.00
clkmgr_sec_cm 3.370s 547.412us 2 5 40.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.410s 108.581us 20 20 100.00
prim_count_check 2 5 40.00
clkmgr_sec_cm 3.370s 547.412us 2 5 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 7.180s 1477.836us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 149.530s 22462.614us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 16 test runs
clkmgr_shadow_reg_errors 63209905464503118509741887221428114000513037549829245807589420288659274654256 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 57085791234919797151815664433777436011078858165379245464562708022102941261242 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 20004424175536890860915660867487818323118985551076791889772775545019631148333 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 82007360688216470283276929867088622480725821809550054252095545709799664866293 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 98734802911729802778208128807387640317498303061813055625347840108013228830394 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 52533244767651445488849771318435955771905084388455780287326916508052721823300 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 65379871672999729276777030596028387909526497958456165492891852622343014653214 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 30793159184688502494131000389369698034752052301330737471286612793388892835530 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 105818325027170408290846421013041620859594852834577131884725194602308762760238 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 25595591711157874577591448977548897751852452028994880417678069963223344038737 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 23056219974163471169901641958238312146763126107960496020546352070801204360455 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 19522801122241776674358354104618912069695125819722271944502318284683005463963 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 102023741605721608297616941112754813658798848476768209224619695785739089267750 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 65149982102220456467678402948686281626866501075915585480222979865850075914887 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 67554373946740325140141152694055581887491626431795997192492325571677076026619 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 42828431916666952490708413739291680455826894675494132368867598433888376793062 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1030) [clkmgr_common_vseq] timeout wait for alert handshake:fatal_fault 11 test runs
clkmgr_tl_intg_err 5019200586824842624267504281875191466053833950272466591936386755620185768234 109
UVM_INFO @ 10042711770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 82354683871118476990494326945562488207214368660837931008363294648872097987100 119
UVM_INFO @ 10069927234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 84469879235659295752293126775618814824136558982052712710174695576139768912491 172
UVM_INFO @ 10218794526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 42384349780420468265850436091408346444491866296591420636828193849515252020100 101
UVM_INFO @ 10016935498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 63467479311320967651997590820218623853803878808138327176577521406097533957479 219
UVM_INFO @ 10173805293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 63439513324507597077355745367885190265964041766277856705131475295386488848960 116
UVM_INFO @ 10076984955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 71312625581549906859419053401335931143789012630837359495296350842864595360296 108
UVM_INFO @ 10020363158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 41929470171351360606445071241409048151912931418009346711418473346355157572596 120
UVM_INFO @ 10077237509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 94470310991204735957187781810719014802712849021185415556391033463663375602223 124
UVM_INFO @ 10122289734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 53015152522414375012671870990194599343454092708211769979248325642979696520513 94
UVM_INFO @ 10040598941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 73544545900330519341666601672035547986698985087091624518501704402737429372836 141
UVM_INFO @ 10170777977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 3 test runs
clkmgr_shadow_reg_errors_with_csr_rw 39708557396467476586872931504163337260164639714195117579724983839184432987013 76
UVM_INFO @ 89030573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 56180923370524172641742460760021936625168007645634622758671689607256081061919 76
UVM_INFO @ 59820031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 60151991540228014557879018332535746203237429792023362962012862942186273242685 75
UVM_INFO @ 5509618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire 3 test runs
clkmgr_sec_cm 20622855001315401365681068620125670225074237668158181776085215031044947775969 84
UVM_INFO @ 13044664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 55283334513129746306594634883511003536772732471158847103180076777908690779513 96
UVM_INFO @ 38894768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 5189417091442915153978594926850966357305991028882236014396774740472437515687 82
UVM_INFO @ 18933666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 2 test runs
clkmgr_clk_handshake_intersig_mubi 61352331611265606285894806505350344105566159069492563108510211989066386003632 74
UVM_INFO @ 9242978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 112086120791995389711914764120266501338261817979499133826739524576957370873250 74
UVM_INFO @ 12056392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: clkmgr_reg_block.fatal_err_code.shadow_storage_err reset value: * Check_csr_read_clear_staged_val task: check storage_err status 2 test runs
clkmgr_shadow_reg_errors_with_csr_rw 68817323375290042018538323429166698412822065068050913218882526309555780922221 75
UVM_INFO @ 30636584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 104424920360210411450076276048683488625624984605540561049507088980250233884726 75
UVM_INFO @ 78910060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 73511742381778881345777293290127431040084482811926836928879763980840604184990 75
UVM_INFO @ 2062694020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---