Simulation Results

Simulation Results: csrng

16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.13 %

code
96.26 %

assert
95.85 %

func
90.27 %

block
98.62 %

line
99.61 %

branch
96.55 %

toggle
93.64 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		96.33%
V2S		99.70%
V3		0.00%

105/105 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	csrng_smoke	32.000s	42.954us	50	50	100.00
csr_hw_reset				5	5	100.00
	csrng_csr_hw_reset	33.000s	134.875us	5	5	100.00
csr_rw				20	20	100.00
	csrng_csr_rw	32.000s	47.210us	20	20	100.00
csr_bit_bash				5	5	100.00
	csrng_csr_bit_bash	39.000s	363.931us	5	5	100.00
csr_aliasing				5	5	100.00
	csrng_csr_aliasing	35.000s	168.991us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	csrng_csr_mem_rw_with_rand_reset	32.000s	39.211us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	csrng_csr_rw	32.000s	47.210us	20	20	100.00
	csrng_csr_aliasing	35.000s	168.991us	5	5	100.00

1416/1470 passed

96.33 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				199	200	99.50
	csrng_intr	288.000s	10007.894us	199	200	99.50
alerts				500	500	100.00
	csrng_alert	50.000s	4124.757us	500	500	100.00
err				500	500	100.00
	csrng_err	33.000s	67.241us	500	500	100.00
cmds				1	50	2.00
	csrng_cmds	98.000s	5846.830us	1	50	2.00
life cycle				1	50	2.00
	csrng_cmds	98.000s	5846.830us	1	50	2.00
stress_all				47	50	94.00
	csrng_stress_all	831.000s	41122.796us	47	50	94.00
intr_test				50	50	100.00
	csrng_intr_test	32.000s	30.003us	50	50	100.00
alert_test				50	50	100.00
	csrng_alert_test	32.000s	112.043us	50	50	100.00
tl_d_oob_addr_access				19	20	95.00
	csrng_tl_errors	262.000s	10000.831us	19	20	95.00
tl_d_illegal_access				19	20	95.00
	csrng_tl_errors	262.000s	10000.831us	19	20	95.00
tl_d_outstanding_access				50	50	100.00
	csrng_csr_hw_reset	33.000s	134.875us	5	5	100.00
	csrng_csr_rw	32.000s	47.210us	20	20	100.00
	csrng_csr_aliasing	35.000s	168.991us	5	5	100.00
	csrng_same_csr_outstanding	32.000s	25.686us	20	20	100.00
tl_d_partial_access				50	50	100.00
	csrng_csr_hw_reset	33.000s	134.875us	5	5	100.00
	csrng_csr_rw	32.000s	47.210us	20	20	100.00
	csrng_csr_aliasing	35.000s	168.991us	5	5	100.00
	csrng_same_csr_outstanding	32.000s	25.686us	20	20	100.00

V2S

1341/1345 passed

99.70 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				25	25	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
	csrng_tl_intg_err	35.000s	284.848us	20	20	100.00
sec_cm_config_regwen				70	70	100.00
	csrng_regwen	32.000s	14.855us	50	50	100.00
	csrng_csr_rw	32.000s	47.210us	20	20	100.00
sec_cm_config_mubi				500	500	100.00
	csrng_alert	50.000s	4124.757us	500	500	100.00
sec_cm_intersig_mubi				47	50	94.00
	csrng_stress_all	831.000s	41122.796us	47	50	94.00
sec_cm_main_sm_fsm_sparse				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_cmd_stage_fsm_sparse				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_ctr_drbg_fsm_sparse				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_ctr_drbg_ctr_redun				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_gen_cmd_ctr_redun				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_ctrl_mubi				500	500	100.00
	csrng_alert	50.000s	4124.757us	500	500	100.00
sec_cm_main_sm_ctr_local_esc				699	700	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
sec_cm_constants_lc_gated				47	50	94.00
	csrng_stress_all	831.000s	41122.796us	47	50	94.00
sec_cm_sw_genbits_bus_consistency				500	500	100.00
	csrng_alert	50.000s	4124.757us	500	500	100.00
sec_cm_tile_link_bus_integrity				20	20	100.00
	csrng_tl_intg_err	35.000s	284.848us	20	20	100.00
sec_cm_aes_cipher_fsm_sparse				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_aes_cipher_fsm_redun				699	700	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
sec_cm_aes_cipher_ctrl_sparse				699	700	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
sec_cm_aes_cipher_fsm_local_esc				699	700	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
sec_cm_aes_cipher_ctr_redun				704	705	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00
	csrng_sec_cm	34.000s	273.917us	5	5	100.00
sec_cm_aes_cipher_data_reg_local_esc				699	700	99.86
	csrng_intr	288.000s	10007.894us	199	200	99.50
	csrng_err	33.000s	67.241us	500	500	100.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	10802.058s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (csrng_scoreboard.sv:660) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [] vs [*])				44 test runs
	csrng_cmds	44391887237586734069650072308031377055504961518014917612916143679599796603712	130	UVM_INFO @ 177111126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65098254918431522617476742143987177478425173397327317332386566627909637250730	140	UVM_INFO @ 307039653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46033583807057176866706553500538437034069626202870329396871548703453032842182	130	UVM_INFO @ 315696385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	96380786745820116276745757731778214300444887961206533709168318816448144676399	130	UVM_INFO @ 124787294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	104585775718330522544955195817206844857629895441661085363975884542158908986366	130	UVM_INFO @ 446834117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99228295997352025518615458542237356008430575837939685975590584743114402474773	130	UVM_INFO @ 83886079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	110534492484703189894302676208746598965661056344780857267067379894138444894419	140	UVM_INFO @ 394235843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	37853849342749391511362806216146592815657321705042432506479436482981967305908	130	UVM_INFO @ 337205386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	65217677783378013355026390321180038119819496099533586802889718445256561971493	130	UVM_INFO @ 42953404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	57548557511562702511472060143757791316277434811615287316180214243147985850713	139	UVM_INFO @ 349012777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	52993327081585090378308757799778184019542380306488143859780023594774106925458	130	UVM_INFO @ 208879206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	75232222562077456505615664233956664339238239038695945030812462645157037423971	130	UVM_INFO @ 43146396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	80532875053043077128556994248290381873524275558493781085242160337530662818668	140	UVM_INFO @ 219501781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	3070100441963960598411904084733034309377782462240173318924238969514166241504	130	UVM_INFO @ 266146954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	13222327732225976981376738052224819625444990949854239757906800191448098093000	130	UVM_INFO @ 61384768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	81920074336659298094116449376987987876644093068344456173431782327571823348097	130	UVM_INFO @ 48144237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	53932875629845334756040019382603226748283489597892282837560132856890049005020	130	UVM_INFO @ 40894445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	54118362693769237031385526794417007198247106337652396105207544217975921948975	130	UVM_INFO @ 187935475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55722295800961688670461146165179089255329443960175284015488717421301488865798	130	UVM_INFO @ 337337561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	114312543788558689699740041814863200673647808205829829398522733910966718834012	130	UVM_INFO @ 49621104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	104025026039326526952075979162170238845879705112399098926682628602745909041398	130	UVM_INFO @ 267243976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	70225054328354486482361670304347740389613170399701748616309685693926283032211	130	UVM_INFO @ 48219809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	31983209133158374241128028281136766598528298646126391796226684480111636167353	140	UVM_INFO @ 204588535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	104328696657510863050185682185741335893056273857518930932797880043746524681151	130	UVM_INFO @ 129561046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	88646790232175282224309242277978073274621794172030895484311018820685782588153	130	UVM_INFO @ 58362474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	32630886372069617556583176919338731554408497544099405620929174780910217279486	130	UVM_INFO @ 561233898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68952748615020131160275584473572546245867721159482997247516809585561253151685	130	UVM_INFO @ 27940176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	90322510909338989601876764912214080787608280321384645331693175841894034474113	130	UVM_INFO @ 152640797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	77291188217535094354409885671784542956576533453593922370457440676253639561295	130	UVM_INFO @ 46841261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	17044484252956305830971378884362473038859024131187768330266541311566248719994	130	UVM_INFO @ 103618255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	62069759203450785664806498805263635963763172979719072800465815272835843914626	130	UVM_INFO @ 637379967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	38110952179132939548543192952529279777759670390322392693805540204845697398866	140	UVM_INFO @ 86599432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	23777140746873570519106797675880162658660872635487629121216854604072537351305	130	UVM_INFO @ 73804423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46350732102340744798804881112313487134989470430296436998850896729262309550511	130	UVM_INFO @ 128077493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	46592814358750924211217993007967900305546750744429213346478493997121576220371	130	UVM_INFO @ 305132476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	76584747756221674836205110622500891140608278554787365964778838192927762219921	130	UVM_INFO @ 101870622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	6749737530142233371367664650597637103974703666207657006732533652217051132741	130	UVM_INFO @ 13035152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	47762849793715008753155750102706391590815520400931218958794229910823551456227	130	UVM_INFO @ 127806117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	99810941699490098584467076938460290346022776055088147637620739651200739265015	130	UVM_INFO @ 244979552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	100176166867856393546930317757740714596552741255904758758548928839776699930304	130	UVM_INFO @ 281201828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	7353794128109927359486303433565674212943648303819018009444348787466618562066	130	UVM_INFO @ 348655554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	25978269257140000554787634651089982062890155750583782363057501596309383591548	130	UVM_INFO @ 30516865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	68642656391504817011740531364749111769736979509490385491544364779419643602756	130	UVM_INFO @ 84749797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	55276181221455194616807602660566111876130327228164376783223935584079031158429	130	UVM_INFO @ 1181289548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				8 test runs
	csrng_stress_all_with_rand_reset	47950204879871590122044011764764011050042140668454976111408281878029252684756	None
	csrng_stress_all_with_rand_reset	35731387398977694133968388151610747665745280771366955550259448679092740080576	None
	csrng_stress_all_with_rand_reset	43229122356467789861682202911204071768705704893079897799979653465748486119423	None
	csrng_stress_all_with_rand_reset	110379118452786464432347637597151403695258617055323498499086331380999392772428	None
	csrng_stress_all_with_rand_reset	12743751083615543265969928078119470893804290394535549254036650127102965956179	None
	csrng_stress_all_with_rand_reset	41063800927159344200963725646066799530831926244047564900984878066133008483942	None
	csrng_stress_all_with_rand_reset	16209722262547460749349322188704611898444313507924881204034872736259528244926	None
	csrng_stress_all_with_rand_reset	87007359933025344698387052660843271709595000055473715709867455580391245170938	None
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [] vs [*]) Interrupt_pin: EntropyReq				3 test runs
	csrng_stress_all	9649181648047253849857725391989743955737754056040792657512510849179385828682	145	UVM_INFO @ 41122796427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	90805508583039579328702977278047978669917675257799346692939379118829392773943	138	UVM_INFO @ 16894171943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all	110084124439484475173335942972571622221396705968509969449706915232356317150013	152	UVM_INFO @ 3797183682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started				2 test runs
	csrng_stress_all_with_rand_reset	51438221767837672526456363499491536416642273115097723395336207247694468125224	111	UVM_INFO @ 3924120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_stress_all_with_rand_reset	73077814667868617247984401184725719260242722019840567834179230441044245683000	120	UVM_INFO @ 30078283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:418) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: csrng_reg_block.genbits				2 test runs
	csrng_cmds	43922034835007028170031336543163467657951080482850680449442623196815676124972	133	UVM_INFO @ 82802945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	23575390825921606260115400122664320471151134733054548400542958422938746637516	133	UVM_INFO @ 139647236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [] vs [*]) alert recov_alert triggered unexpectedly				2 test runs
	csrng_cmds	79162430227071164082238145386428825746589093898987942253366875175172115136750	138	UVM_INFO @ 94900874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	csrng_cmds	86904694547279986572249848932724790568162730019506604120584876813167273758017	138	UVM_INFO @ 71262428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [csrng_common_vseq] wait timeout occurred!				1 test run
	csrng_tl_errors	31470333727429278936211457958383783447551483437420981109516640248897006106345	100	UVM_INFO @ 10000830573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csrng_scoreboard.sv:629) [scoreboard] Check failed cs_item[app].status == cmd_sts[app] (* [] vs [*])				1 test run
	csrng_cmds	9775844582941667557187030728682588541031068987037355352441669836853419616353	139	UVM_INFO @ 239613123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [csrng_intr_vseq] wait timeout occurred!				1 test run
	csrng_intr	31568129794171107506588562497435819790996261080809989808896770338933725365176	129	UVM_INFO @ 10007893655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---