Simulation Results: edn/edn0

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.54 %
  • code
  • 95.95 %
  • assert
  • 97.61 %
  • func
  • 93.06 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 94.14 %
  • toggle
  • 97.17 %
  • FSM
  • 93.01 %
Validation stages
V1
100.00%
V2
99.48%
V2S
100.00%
V3
82.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.380s 21.576us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.150s 39.920us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.380s 32.341us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 5.410s 251.981us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.540s 40.869us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.520s 30.673us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.380s 32.341us 20 20 100.00
edn_csr_aliasing 1.540s 40.869us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 82.950s 8821.767us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 82.950s 8821.767us 300 300 100.00
genbits 300 300 100.00
edn_genbits 82.950s 8821.767us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.300s 21.062us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.510s 56.204us 200 200 100.00
errs 100 100 100.00
edn_err 1.400s 100.862us 100 100 100.00
disable 95 100 95.00
edn_disable 1.390s 37.545us 50 50 100.00
edn_disable_auto_req_mode 4.520s 500.000us 45 50 90.00
stress_all 50 50 100.00
edn_stress_all 8.220s 620.503us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.230s 34.091us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.340s 26.708us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.780s 155.854us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.780s 155.854us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.150s 39.920us 5 5 100.00
edn_csr_rw 1.380s 32.341us 20 20 100.00
edn_csr_aliasing 1.540s 40.869us 5 5 100.00
edn_same_csr_outstanding 1.610s 38.157us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.150s 39.920us 5 5 100.00
edn_csr_rw 1.380s 32.341us 20 20 100.00
edn_csr_aliasing 1.540s 40.869us 5 5 100.00
edn_same_csr_outstanding 1.610s 38.157us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 9.400s 805.905us 5 5 100.00
edn_tl_intg_err 3.500s 211.000us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.340s 19.019us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.510s 56.204us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.400s 805.905us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 9.400s 805.905us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 9.400s 805.905us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 9.400s 805.905us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.510s 56.204us 200 200 100.00
edn_sec_cm 9.400s 805.905us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.510s 56.204us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 3.500s 211.000us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 41 50 82.00
edn_stress_all_with_rand_reset 134.190s 19587.658us 41 50 82.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 9 test runs
edn_stress_all_with_rand_reset 13901988336953447474867970626601858230236132299768737174018960373467959840225 133
UVM_INFO @ 1051377000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 50542617028865442471272661881366697270419525805359297329470483675923046972060 220
UVM_INFO @ 3330064712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 12607081564861474575227396785218663081422467119532175472225690103074528274971 305
UVM_INFO @ 1700232662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 28654234549731768650947889888751731837427126839177615326731326672632174172713 294
UVM_INFO @ 1949886482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 24762098295880937829026932482254727108778649811453508650121744798720522872830 184
UVM_INFO @ 2385418337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 16330380756269992370048636936298020484773403651993594619832788746840093748870 166
UVM_INFO @ 1986464235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 75393569943505045047926656915446478163602972335656307295939768895953544335067 162
UVM_INFO @ 1761868624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 61972834486395219417294622668802979187308644306360238707701213681849833851641 288
UVM_INFO @ 2441326497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 87092494934550636345448069731987809776934751984113034517123944321229870012791 235
UVM_INFO @ 2418926950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 2 test runs
edn_disable_auto_req_mode 28975392542228470972544058219126324445863627561212705880340443694714417182084 88
UVM_INFO @ 8494051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 54566227362975217376450498659319860791741226294452531814220786648942394349710 88
UVM_INFO @ 41132656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
edn_disable_auto_req_mode 25343793538989872065410156320632492463359074724372918264921084795237212340518 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 57767016104499219458838650140889663921053053192642189029443049227108473318468 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *. 1 test run
edn_disable_auto_req_mode 94118207012768327918040605831289932874719892664511647479304212347632435713819 88
UVM_INFO @ 100882923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---