Simulation Results: edn/edn1

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.25 %
  • code
  • 96.18 %
  • assert
  • 97.14 %
  • func
  • 92.44 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.08 %
  • toggle
  • 96.15 %
  • FSM
  • 96.59 %
Validation stages
V1
100.00%
V2
99.07%
V2S
100.00%
V3
82.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 0.920s 28.505us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.900s 32.013us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.960s 149.164us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.190s 254.259us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.060s 27.199us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.390s 175.303us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.960s 149.164us 20 20 100.00
edn_csr_aliasing 1.060s 27.199us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 55.330s 4380.376us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 55.330s 4380.376us 300 300 100.00
genbits 300 300 100.00
edn_genbits 55.330s 4380.376us 300 300 100.00
interrupts 50 50 100.00
edn_intr 0.990s 28.668us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.250s 426.319us 200 200 100.00
errs 100 100 100.00
edn_err 1.090s 29.760us 100 100 100.00
disable 91 100 91.00
edn_disable 0.940s 17.402us 50 50 100.00
edn_disable_auto_req_mode 7.090s 500.000us 41 50 82.00
stress_all 50 50 100.00
edn_stress_all 6.640s 352.442us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.890s 59.468us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 0.890s 28.069us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 2.760s 280.688us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 2.760s 280.688us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.900s 32.013us 5 5 100.00
edn_csr_rw 0.960s 149.164us 20 20 100.00
edn_csr_aliasing 1.060s 27.199us 5 5 100.00
edn_same_csr_outstanding 1.350s 32.577us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.900s 32.013us 5 5 100.00
edn_csr_rw 0.960s 149.164us 20 20 100.00
edn_csr_aliasing 1.060s 27.199us 5 5 100.00
edn_same_csr_outstanding 1.350s 32.577us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 3.770s 1040.054us 5 5 100.00
edn_tl_intg_err 4.490s 451.254us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.870s 17.989us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.250s 426.319us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.770s 1040.054us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.770s 1040.054us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.770s 1040.054us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.770s 1040.054us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.250s 426.319us 200 200 100.00
edn_sec_cm 3.770s 1040.054us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.250s 426.319us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 4.490s 451.254us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 41 50 82.00
edn_stress_all_with_rand_reset 123.930s 24285.036us 41 50 82.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 7 test runs
edn_stress_all_with_rand_reset 63912233444950711537039491928209993511921933436055925279964324231762305371132 203
UVM_INFO @ 1123974260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 82677930977419812905006536987225796723222784228319110841995176390653850392263 144
UVM_INFO @ 1327507970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 69383062795165189469414921843698900822620833437751344114638127976701069911812 168
UVM_INFO @ 1593171936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 18292534686045849135001152570352984336975865619042763833124921244105502621757 146
UVM_INFO @ 114305546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 43398545444855934102544740489003082440033238914069351315951234866963311315880 113
UVM_INFO @ 119605808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 51258569368074747679849584157609859381453713670732661318644362501759438496835 178
UVM_INFO @ 1568065391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 13688193125257052760389536592465049449574036987434264327928966522871680110907 316
UVM_INFO @ 3676593606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 5 test runs
edn_disable_auto_req_mode 102497994047053862198877144014029396384113870605799143716526856839453588308383 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 89393274000648411763521478659982602934378658107764746846869171748111065320129 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 10680866548659647281836446199222474387881993947333415036098140639616826762407 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 77486110013160196823970305527154277672993487202416450325644314355315072020350 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109218100878718098445873099173547996979760463382959301374132881334751048764698 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 4 test runs
edn_disable_auto_req_mode 112402730836009899859052272873914137323050380498902894609811246449186048337086 88
UVM_INFO @ 78312659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 82208437437031072774634249401780402000586270289186216556493621415651303230664 88
UVM_INFO @ 24262008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 63371338439145450805425082687931020171174637029019626192618966067330951245018 88
UVM_INFO @ 32694798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 37116541543063883631430480624015541469099840846268958598494703006450013636194 88
UVM_INFO @ 123393716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [edn_common_vseq] wait timeout occurred! 2 test runs
edn_stress_all_with_rand_reset 80578896804090154573039505222468317289471006376211499334484778792154806714627 137
UVM_INFO @ 13202348863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 73067861308204364961026556457352329273692681422674240504735533238888420440225 126
UVM_INFO @ 10006935687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---