Simulation Results

Simulation Results: flash_ctrl

16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
97.04 %

code
95.91 %

assert
96.84 %

func
98.36 %

line
96.10 %

branch
97.45 %

cond
94.83 %

toggle
98.66 %

FSM
92.52 %

Validation stages

V1		99.17%
V2		98.85%
V2S		99.38%
V3		100.00%
unmapped		100.00%

119/120 passed

99.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	flash_ctrl_smoke	155.020s	99.064us	50	50	100.00
smoke_hw				5	5	100.00
	flash_ctrl_smoke_hw	29.420s	85.358us	5	5	100.00
csr_hw_reset				5	5	100.00
	flash_ctrl_csr_hw_reset	33.880s	109.743us	5	5	100.00
csr_rw				20	20	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
csr_bit_bash				5	5	100.00
	flash_ctrl_csr_bit_bash	80.600s	6191.636us	5	5	100.00
csr_aliasing				5	5	100.00
	flash_ctrl_csr_aliasing	63.180s	1723.467us	5	5	100.00
csr_mem_rw_with_rand_reset				19	20	95.00
	flash_ctrl_csr_mem_rw_with_rand_reset	33.920s	10036.130us	19	20	95.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
	flash_ctrl_csr_aliasing	63.180s	1723.467us	5	5	100.00
mem_walk				5	5	100.00
	flash_ctrl_mem_walk	12.460s	29.401us	5	5	100.00
mem_partial_access				5	5	100.00
	flash_ctrl_mem_partial_access	15.150s	135.696us	5	5	100.00

1031/1043 passed

98.85 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sw_op				5	5	100.00
	flash_ctrl_sw_op	22.500s	26.914us	5	5	100.00
host_read_direct				5	5	100.00
	flash_ctrl_host_dir_rd	83.480s	63.920us	5	5	100.00
rma_hw_if				43	43	100.00
	flash_ctrl_hw_rma	1493.660s	376920.298us	3	3	100.00
	flash_ctrl_hw_rma_reset	833.030s	190213.715us	20	20	100.00
	flash_ctrl_lcmgr_intg	15.270s	96.954us	20	20	100.00
host_controller_arb				4	5	80.00
	flash_ctrl_host_ctrl_arb	1909.750s	280409.524us	4	5	80.00
erase_suspend				5	5	100.00
	flash_ctrl_erase_suspend	383.290s	3354.557us	5	5	100.00
program_reset				29	30	96.67
	flash_ctrl_prog_reset	3604.011s	0.000us	29	30	96.67
full_memory_access				5	5	100.00
	flash_ctrl_full_mem_access	4480.630s	698428.028us	5	5	100.00
rd_buff_eviction				5	5	100.00
	flash_ctrl_rd_buff_evict	90.560s	736.188us	5	5	100.00
rd_buff_eviction_w_ecc				98	100	98.00
	flash_ctrl_rw_evict	35.770s	28.894us	38	40	95.00
	flash_ctrl_rw_evict_all_en	35.120s	29.492us	40	40	100.00
	flash_ctrl_re_evict	35.340s	124.683us	20	20	100.00
host_arb				20	20	100.00
	flash_ctrl_phy_arb	243.030s	2027.819us	20	20	100.00
host_interleave				20	20	100.00
	flash_ctrl_phy_arb	243.030s	2027.819us	20	20	100.00
memory_protection				20	20	100.00
	flash_ctrl_mp_regions	599.630s	45413.259us	20	20	100.00
fetch_code				10	10	100.00
	flash_ctrl_fetch_code	30.670s	3286.741us	10	10	100.00
all_partitions				20	20	100.00
	flash_ctrl_rand_ops	888.930s	816.432us	20	20	100.00
error_mp				10	10	100.00
	flash_ctrl_error_mp	805.350s	44200.538us	10	10	100.00
error_prog_win				10	10	100.00
	flash_ctrl_error_prog_win	565.670s	13982.577us	10	10	100.00
error_prog_type				5	5	100.00
	flash_ctrl_error_prog_type	1830.520s	1144.464us	5	5	100.00
error_read_seed				20	20	100.00
	flash_ctrl_hw_read_seed_err	14.730s	299.980us	20	20	100.00
read_write_overflow				5	5	100.00
	flash_ctrl_oversize_error	182.960s	7259.034us	5	5	100.00
flash_ctrl_disable				50	50	100.00
	flash_ctrl_disable	23.550s	58.646us	50	50	100.00
flash_ctrl_connect				80	80	100.00
	flash_ctrl_connect	18.650s	53.685us	80	80	100.00
stress_all				5	5	100.00
	flash_ctrl_stress_all	1107.710s	344.372us	5	5	100.00
secret_partition				129	130	99.23
	flash_ctrl_hw_sec_otp	231.650s	45340.856us	49	50	98.00
	flash_ctrl_otp_reset	111.780s	145.484us	80	80	100.00
isolation_partition				3	3	100.00
	flash_ctrl_hw_rma	1493.660s	376920.298us	3	3	100.00
interrupts				95	100	95.00
	flash_ctrl_intr_rd	202.250s	4238.767us	36	40	90.00
	flash_ctrl_intr_wr	3604.012s	0.000us	9	10	90.00
	flash_ctrl_intr_rd_slow_flash	379.420s	30867.150us	40	40	100.00
	flash_ctrl_intr_wr_slow_flash	450.580s	223889.437us	10	10	100.00
invalid_op				20	20	100.00
	flash_ctrl_invalid_op	75.760s	3356.045us	20	20	100.00
mid_op_rst				5	5	100.00
	flash_ctrl_mid_op_rst	59.340s	1644.397us	5	5	100.00
double_bit_err				34	35	97.14
	flash_ctrl_read_word_sweep_derr	22.010s	147.709us	5	5	100.00
	flash_ctrl_ro_derr	124.350s	13612.363us	10	10	100.00
	flash_ctrl_rw_derr	217.750s	4400.057us	10	10	100.00
	flash_ctrl_derr_detect	162.960s	2698.528us	5	5	100.00
	flash_ctrl_integrity	3603.296s	0.000us	4	5	80.00
single_bit_err				25	25	100.00
	flash_ctrl_read_word_sweep_serr	23.190s	47.871us	5	5	100.00
	flash_ctrl_ro_serr	124.410s	681.747us	10	10	100.00
	flash_ctrl_rw_serr	218.030s	2193.873us	10	10	100.00
singlebit_err_counter				5	5	100.00
	flash_ctrl_serr_counter	104.310s	2713.607us	5	5	100.00
singlebit_err_address				5	5	100.00
	flash_ctrl_serr_address	100.890s	5178.832us	5	5	100.00
scramble				61	62	98.39
	flash_ctrl_wo	217.790s	46802.094us	20	20	100.00
	flash_ctrl_write_word_sweep	8.340s	79.703us	1	1	100.00
	flash_ctrl_read_word_sweep	8.430s	81.112us	1	1	100.00
	flash_ctrl_ro	110.540s	831.989us	20	20	100.00
	flash_ctrl_rw	3603.392s	0.000us	19	20	95.00
filesystem_support				5	5	100.00
	flash_ctrl_fs_sup	38.390s	396.765us	5	5	100.00
rma_write_process_error				23	23	100.00
	flash_ctrl_rma_err	887.410s	171155.884us	3	3	100.00
	flash_ctrl_hw_prog_rma_wipe_err	159.610s	10019.201us	20	20	100.00
alert_test				50	50	100.00
	flash_ctrl_alert_test	14.840s	50.844us	50	50	100.00
intr_test				50	50	100.00
	flash_ctrl_intr_test	15.270s	18.283us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	flash_ctrl_tl_errors	20.060s	94.738us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	flash_ctrl_tl_errors	20.060s	94.738us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	flash_ctrl_csr_hw_reset	33.880s	109.743us	5	5	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
	flash_ctrl_csr_aliasing	63.180s	1723.467us	5	5	100.00
	flash_ctrl_same_csr_outstanding	30.920s	204.285us	20	20	100.00
tl_d_partial_access				50	50	100.00
	flash_ctrl_csr_hw_reset	33.880s	109.743us	5	5	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
	flash_ctrl_csr_aliasing	63.180s	1723.467us	5	5	100.00
	flash_ctrl_same_csr_outstanding	30.920s	204.285us	20	20	100.00

V2S

482/485 passed

99.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	flash_ctrl_shadow_reg_errors_with_csr_rw	121.210s	109.658us	20	20	100.00
tl_intg_err				25	25	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
	flash_ctrl_tl_intg_err	531.910s	3195.545us	20	20	100.00
sec_cm_reg_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	531.910s	3195.545us	20	20	100.00
sec_cm_host_bus_integrity				20	20	100.00
	flash_ctrl_tl_intg_err	531.910s	3195.545us	20	20	100.00
sec_cm_mem_bus_integrity				6	6	100.00
	flash_ctrl_rd_intg	21.310s	77.911us	3	3	100.00
	flash_ctrl_wr_intg	15.170s	59.158us	3	3	100.00
sec_cm_scramble_key_sideload				50	50	100.00
	flash_ctrl_smoke	155.020s	99.064us	50	50	100.00
sec_cm_lc_ctrl_intersig_mubi				260	260	100.00
	flash_ctrl_otp_reset	111.780s	145.484us	80	80	100.00
	flash_ctrl_disable	23.550s	58.646us	50	50	100.00
	flash_ctrl_sec_info_access	82.140s	11029.796us	50	50	100.00
	flash_ctrl_connect	18.650s	53.685us	80	80	100.00
sec_cm_ctrl_config_regwen				5	5	100.00
	flash_ctrl_config_regwen	14.510s	22.137us	5	5	100.00
sec_cm_data_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
sec_cm_data_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
sec_cm_info_regions_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
sec_cm_info_regions_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
sec_cm_bank_config_regwen				20	20	100.00
	flash_ctrl_csr_rw	19.630s	521.796us	20	20	100.00
sec_cm_bank_config_shadow				20	20	100.00
	flash_ctrl_shadow_reg_errors	70.920s	125.618us	20	20	100.00
sec_cm_mem_ctrl_global_esc				50	50	100.00
	flash_ctrl_disable	23.550s	58.646us	50	50	100.00
sec_cm_mem_ctrl_local_esc				6	6	100.00
	flash_ctrl_rd_intg	21.310s	77.911us	3	3	100.00
	flash_ctrl_access_after_disable	14.280s	36.654us	3	3	100.00
sec_cm_mem_addr_infection				3	3	100.00
	flash_ctrl_host_addr_infection	26.070s	65.395us	3	3	100.00
sec_cm_mem_disable_config_mubi				50	50	100.00
	flash_ctrl_disable	23.550s	58.646us	50	50	100.00
sec_cm_exec_config_redun				10	10	100.00
	flash_ctrl_fetch_code	30.670s	3286.741us	10	10	100.00
sec_cm_mem_scramble				19	20	95.00
	flash_ctrl_rw	3603.392s	0.000us	19	20	95.00
sec_cm_mem_integrity				24	25	96.00
	flash_ctrl_rw_serr	218.030s	2193.873us	10	10	100.00
	flash_ctrl_rw_derr	217.750s	4400.057us	10	10	100.00
	flash_ctrl_integrity	3603.296s	0.000us	4	5	80.00
sec_cm_rma_entry_mem_sec_wipe				3	3	100.00
	flash_ctrl_hw_rma	1493.660s	376920.298us	3	3	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
sec_cm_phy_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
sec_cm_phy_prog_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
sec_cm_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
sec_cm_phy_arbiter_ctrl_redun				5	5	100.00
	flash_ctrl_phy_arb_redun	23.560s	893.111us	5	5	100.00
sec_cm_phy_host_grant_ctrl_consistency				4	5	80.00
	flash_ctrl_phy_host_grant_err	13.320s	40.151us	4	5	80.00
sec_cm_phy_ack_ctrl_consistency				5	5	100.00
	flash_ctrl_phy_ack_consistency	13.090s	25.472us	5	5	100.00
sec_cm_fifo_ctr_redun				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00
sec_cm_prog_tl_lc_gate_fsm_sparse				5	5	100.00
	flash_ctrl_sec_cm	2534.290s	1302.739us	5	5	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
asymmetric_read_path				1	1	100.00
	flash_ctrl_rd_ooo	26.880s	32.500us	1	1	100.00

unmapped

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				3	3	100.00
	flash_ctrl_basic_rw	390.330s	1964.976us	3	3	100.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				4 test runs
	flash_ctrl_integrity	37399064998885902962375332805027807624421551520111586861751912714467415687071	None
	flash_ctrl_intr_wr	81126352728323287913051843372801378421086910019826790445513653118249086037100	None
	flash_ctrl_prog_reset	17346534485126846086968623186900291687504756926029441212109776786698667608617	None
	flash_ctrl_rw	7803771482035031904970778431554975585017421374391320337042633869555954388685	None
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: flash_ctrl_core_reg_block.op_status.err reset value:				2 test runs
	flash_ctrl_rw_evict	85301798694672809998796788718415950462499213211005141838062049477241333319745	108	UVM_INFO @ 9141.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	flash_ctrl_rw_evict	39668186498736361824196967826702210962928878419578235910290953939548703374637	108	UVM_INFO @ 18662.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_env_cfg.sv:714) [cfg] Check failed data[i] === exp_data[i] (* [] vs [*])				1 test run
	flash_ctrl_host_ctrl_arb	57508428887412896336359752681628534862758052437632266924050759242944373132249	216	UVM_INFO @ 56389478.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [flash_ctrl_common_vseq] wait timeout occurred!				1 test run
	flash_ctrl_csr_mem_rw_with_rand_reset	72516299725765050917299761727067400300003929761151930538497622978879746689779	115	UVM_INFO @ 10036130.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'				1 test run
	flash_ctrl_phy_host_grant_err	3616026656389566631207641974111984393709725995061064054850919026449959946781	125	UVM_ERROR @ 5727.7 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A UVM_INFO @ 5727.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [flash_ctrl_hw_sec_otp_vseq] wait timeout occurred!				1 test run
	flash_ctrl_hw_sec_otp	50481267541331462523030786812760951900873265615954986478088194417083352687967	108	UVM_INFO @ 10002795.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp f94cf0_abefe9e2:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	100775254208798971881005404952622694192956531150667366333201305098916259340418	108	UVM_INFO @ 1545955.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp ea15b5c_bd564723:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	59288369915355975663287965893121265730511671815917193620212542431848036411550	108	UVM_INFO @ 1187222.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp ccf84b_4760cd01:ffffffff_4760cd* mismatch!!				1 test run
	flash_ctrl_intr_rd	79028327281133009919361411961792970733512631178194834846249134408401660642976	108	UVM_INFO @ 392056.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] : obs:exp de24195_c8fb2fb0:ffffffff_ffffffff mismatch!!				1 test run
	flash_ctrl_intr_rd	10563316929660110519235064048464274012188803230172773696478075482404008170531	108	UVM_INFO @ 3474680.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---