Simulation Results: gpio

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.37 %
  • code
  • 98.27 %
  • assert
  • 96.84 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 93.94 %
Validation stages
V1
100.00%
V2
93.28%
V2S
100.00%
V3
39.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 1.630s 37.222us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.830s 107.436us 50 50 100.00
gpio_smoke_en_cdc_prim 1.860s 110.917us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.890s 54.727us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 1.030s 71.578us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 0.980s 16.257us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 4.070s 1471.238us 5 5 100.00
csr_aliasing 5 5 100.00
gpio_csr_aliasing 1.250s 33.973us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.860s 129.093us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
gpio_csr_rw 0.980s 16.257us 20 20 100.00
gpio_csr_aliasing 1.250s 33.973us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.720s 126.135us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.690s 126.800us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.370s 89.344us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 1.810s 153.832us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 4.160s 226.154us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 4.040s 93.813us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 19.650s 676.916us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 6.870s 545.212us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.530s 89.026us 50 50 100.00
stress_all 5 50 10.00
gpio_stress_all 90.270s 14309.864us 5 50 10.00
alert_test 50 50 100.00
gpio_alert_test 0.960s 48.897us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.990s 17.713us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 3.910s 978.942us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 3.910s 978.942us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
gpio_csr_rw 0.980s 16.257us 20 20 100.00
gpio_same_csr_outstanding 1.290s 149.392us 20 20 100.00
gpio_csr_aliasing 1.250s 33.973us 5 5 100.00
gpio_csr_hw_reset 1.030s 71.578us 5 5 100.00
tl_d_partial_access 50 50 100.00
gpio_csr_rw 0.980s 16.257us 20 20 100.00
gpio_same_csr_outstanding 1.290s 149.392us 20 20 100.00
gpio_csr_aliasing 1.250s 33.973us 5 5 100.00
gpio_csr_hw_reset 1.030s 71.578us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
gpio_tl_intg_err 1.930s 116.521us 20 20 100.00
gpio_sec_cm 1.400s 303.876us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
gpio_tl_intg_err 1.930s 116.521us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 39 50 78.00
gpio_rand_straps 0.950s 14.766us 39 50 78.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 12.790s 346.566us 0 50 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 56 test runs
gpio_stress_all 62896052911332812871667681306806104500371275817205452158897643606997124327503 804
UVM_INFO @ 1713065934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90122398734498066614096165757343287276233877089321885304767768426637809962520 2877
UVM_INFO @ 3297676032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 65795018665469283710119509652345714929598367819213655106685801448783358223657 1086
UVM_INFO @ 8382559092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 9588853851544630962271424579822510835175913334756008119289832624057448789125 108
UVM_INFO @ 344970957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 73045750227154229153550834866466473026790056631806946443311090010585384194688 1240
UVM_INFO @ 4309265671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 18646587043854905892123788885000135288457830152895874725766518199165607265990 1092
UVM_INFO @ 4967030467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 60491619445217138157144253980455805380587957186228343073956629843830665228791 75
UVM_INFO @ 1643873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 83088033716582692553377501233720321992250812526539542719523491209560094157267 1637
UVM_INFO @ 9972735061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 25139708044074937219802068887842620975452664863173418606626541653105679470784 75
UVM_INFO @ 12858306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10933405020116068640340886813011349889561264013297374041303897715336292592550 76
UVM_INFO @ 9306228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 76301793266834644911187177524576182244817088325796104111968432594625438510637 366
UVM_INFO @ 1290459476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84152667825511577218859965336467703674244202793708024040061662868447473552913 1412
UVM_INFO @ 3461044529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 46095454714909474657200021457841307745023598933882841548167188829078487306661 83
UVM_INFO @ 866831640 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 5797029224002622286912845440454255528064263722486951081000406864065385242166 480
UVM_INFO @ 1000743669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 36659782089320774329501021813233372478637552955606801636311780040980037968337 985
UVM_INFO @ 19001928258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 81422297027211850364893005090286690220460833462199315537839118730467892776064 2958
UVM_INFO @ 2828803375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 97611339847902053653285526085648180763185339747469858540040166425222160737695 682
UVM_INFO @ 1722805621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 29566539923825614734631689388095330903717080172514209724432749373063552404288 75
UVM_INFO @ 5893455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 23268847739803388430526065083026210545262737801007300644607458554350249638864 325
UVM_INFO @ 5977138949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 7586485100055714483325220622005256070254176350766044750486889865603778568461 75
UVM_INFO @ 1672658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 44448306258604277776256976263071916603774061431817098429323818916049296368253 79
UVM_INFO @ 199257403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 41122697231465351554043210120759439053679174498503779961781436534797999123480 75
UVM_INFO @ 4723399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 15664477159726144476482356480413975960400120005928510910623050232634450287716 1420
UVM_INFO @ 5574675771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 89009359116654212148285820275310736026309732080639504899985123041503154814062 221
UVM_INFO @ 1042376190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 114096181261863849794711464778288004344426871566101581942103706605794559509712 909
UVM_INFO @ 2920493760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 8389149497922629780002896995323049595580584347280747156060717695098944899678 79
UVM_INFO @ 1607113651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 104652722554816538751852036443067969059741430634271706972830591500733761704384 75
UVM_INFO @ 5459576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 49384619765987434055609221100274566399402408452829728060956901846075396139161 1878
UVM_INFO @ 3490767525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 23460127268497010632365855181502457432104487684252316119464684121265601210125 838
UVM_INFO @ 2959272157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10137516905280992459377927683371451484568585910456886052087752195037424074591 420
UVM_INFO @ 1091145279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 17698085787735671458778114478433224090106781268143343582644372379805241434708 77
UVM_INFO @ 125009782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 35088398083155501615640382518796759265984778196205298641072671402863527454493 1320
UVM_INFO @ 17134086340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12726333954544419049825516547166430793448273074217345331819230855142505384034 325
UVM_INFO @ 1153273035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 14338794727267845243363167547141776439550994000279848302250566618188487996567 75
UVM_INFO @ 2519279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101022805658179092372021210186014452815560777209385331359967667164214790723668 1957
UVM_INFO @ 9882097703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 55708595193375588766078376605552960686328516336383304664609434546456399693755 1819
UVM_INFO @ 4358327497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 77239969951373514983114503794437581470595924813758699294565493713452088299295 75
UVM_INFO @ 4083497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 62836378219576677981327507112362770772326126421342971318923869629089170065207 224
UVM_INFO @ 7716593306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 95360507231513736352101015994418258610391493843420629901367722945575629665162 807
UVM_INFO @ 2838729639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 32261641685600693932889393080017285433241456364602552537542317760383272866911 2567
UVM_INFO @ 14309864343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 107660881319865396472553751343659411329164902424863095567459014918647878813888 201
UVM_INFO @ 925247662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 54700332400365524904741788989458686770854340176905565193658528424186164222749 79
UVM_INFO @ 580697690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 34756650719533307722235480199531971301049591571168891247878910641839921608639 280
UVM_INFO @ 462464551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 94523206960608807788466835262400569963156419488286441867793444563140056945582 75
UVM_INFO @ 1178598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 52525000668780901585758627346341383333830097837522318316479150486740175358064 1056
UVM_INFO @ 2130476838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 101741335741506886605814684926089171644325033357022848871152142878871710045355 935
UVM_INFO @ 5488701914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 77018943492241936524578582545363628708729913392919936578098985117044291805867 462
UVM_INFO @ 1713879020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 22397275683366845316992516711080707764026965343718505613872918659670823508243 75
UVM_INFO @ 1304643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 92629042609544942955018538856304329657552958426258548317624591774742334632649 888
UVM_INFO @ 8823193736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 10020824488465430621015317247610737712164500424259581299672836625439151550594 1283
UVM_INFO @ 15356883322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 82463179660338976814171512556909313395789683389350890071599431855565967324182 2201
UVM_INFO @ 42547420620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 14622481871320242358353105690848116237143464144277016573586538988810695016440 965
UVM_INFO @ 12100809789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 70483213446017815211082016527439946139497658285144382440850433981868378075150 86
UVM_INFO @ 1827578265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 93928219502070480810601802334599215678627475667956032745250725345864295987530 75
UVM_INFO @ 5646695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 113990169342198010460428707297439374684992698041523056359058602830199664080060 77
UVM_INFO @ 985916537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 49736959712496873205928288830319654621660988307673700416013691641095281697022 1770
UVM_INFO @ 2140471475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 30 test runs
gpio_stress_all_with_rand_reset 12849299332852190309864119410394038212081046059538758873085715836252623965401 83
UVM_INFO @ 7626297147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 5631566090517508884250222658054178535445886575995060453652435893462155087651 166
UVM_INFO @ 269895495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 33056182374865789173345263242310939506373277454438040177678970082202155546499 81
UVM_INFO @ 805487827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 87146655496639413777525185383415062956363053731825603976301840497551661810445 78
UVM_INFO @ 4012534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66992628848088504805581355988837686870527783545959133937791956156183075917735 326
UVM_INFO @ 2208122366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52809567144960887311322001573769592683638888893983410230265246228832682741570 82
UVM_INFO @ 1910389434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30310285160627039905754621997569447228357003108219275759651880479800131943447 227
UVM_INFO @ 766850162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 28819166994600734283286127747053310321906019782320609443592613437139260694237 103
UVM_INFO @ 259029744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 48353855859074476469059161227952875278211969497395295068084083691357653535821 78
UVM_INFO @ 23423402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 3350176998736075897173803378302714511635712405068833031465607073797963120964 78
UVM_INFO @ 2853675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 18743097638626189539047789008494929543442044223855573968686291406969500112453 78
UVM_INFO @ 14391815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66943141585937562122967421007926360966213880601856254044000990179038256035576 78
UVM_INFO @ 467000116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51879968258534643900498077947621017076957192016524235983830314738605407737750 79
UVM_INFO @ 394817250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 4289106291326636743342202481655172280788847956857489012290395501121495195780 226
UVM_INFO @ 1051038395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 27895470898531858270906496024432977850575429936788353908910484543586566178605 78
UVM_INFO @ 10440390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 92086458498886360789203581133429207385820446674468099522452595311633745740054 79
UVM_INFO @ 229002158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 40634655888840427830265210956183656412798022379822044892116751772852449960330 78
UVM_INFO @ 9163852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 115737266924244046412714122308093046543878851416339047904645976119551278082896 112
UVM_INFO @ 329660467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 41339539075805462285630119895379752248391777742213563270681135393549008915952 78
UVM_INFO @ 7252606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58168551139514305427858166403851207233218454783270993097022618909128621235677 78
UVM_INFO @ 26170058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 14795920026604169629027810349656315043335683444925169634538130168357071477087 78
UVM_INFO @ 99109394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39989123779723623001212959276305379267175322402211979916972817680938692253111 118
UVM_INFO @ 124474838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 103081493160199281342059434358069160987697458819322886139443242694943484634477 81
UVM_INFO @ 429231588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 54584623075127116150798344951397189595409288237248953111967003195689181450506 78
UVM_INFO @ 11385858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113389176973633389547648122844724359053256639420946999839431527957855357107301 78
UVM_INFO @ 69725262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 87617353728313622809421814103792396156977776794243336536253740113878207880602 79
UVM_INFO @ 387716361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 47890903869666774144321083302218293082501525538286592399161593775748682428451 81
UVM_INFO @ 313977543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 101030786356425610736638082091215914889230772010680267335146314093359414185964 81
UVM_INFO @ 973511095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51975008566548389224035860587316126674496140756549891911087459387830245259414 78
UVM_INFO @ 164254874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 74513471502421864064310936053698853061683321484565826183580665641282321517618 245
UVM_INFO @ 2771562760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [gpio_common_vseq] Check failed (vseq_done) 20 test runs
gpio_stress_all_with_rand_reset 19139504610123857653451167535895903848368883824759073847667496079725470131010 80
UVM_INFO @ 65781060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 84160398574681821164031115886030434731554020907472449508547249986814716178667 81
UVM_INFO @ 2037639223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 66209145204274086652863564847697243540248792000533731715132983726388597582598 80
UVM_INFO @ 15402738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 12808410594886566422588354340094060829941941930455301006968829764746410208183 227
UVM_INFO @ 1343739396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 73889000926570665321999429415059092938907981538048315984552525823067129657714 160
UVM_INFO @ 1714744834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 32319890936345553878739736012258074089716538663388162908774526790414743165119 85
UVM_INFO @ 346566315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 30383221572661155271069090314495388760588821643208345674471710504175279734608 152
UVM_INFO @ 273355753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6549621325785209572425540417229752891532453709325660910067234062235283468633 80
UVM_INFO @ 1287458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57694475821056150171909250280218058036843561354842175495934558741691164374363 80
UVM_INFO @ 9192109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 95818914828264011099642681453079049340172762909705769564347253633631570524344 80
UVM_INFO @ 5878273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 95344666927400141959535160885725670813283322263807602050138269913084935743659 292
UVM_INFO @ 3516204061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113333493769038204616032359124550110741056764094491735710701881453787236383233 80
UVM_INFO @ 84775088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 102504789971097411688845836073336698090991658833943471300434237306166638550284 88
UVM_INFO @ 32921327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 27753097771243204711555506001306051813970552573210691745341164192316826855407 80
UVM_INFO @ 43353559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39760565710499118213889457833879605848965572406443213062454757724138060744164 119
UVM_INFO @ 1935271816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 79188218008356940629398061976753375273424948060221346726625695350204690793364 84
UVM_INFO @ 30829324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 11352363001219069046270574504727825311007104087143336246883490192139061445327 80
UVM_INFO @ 36037265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 72686421177887680109480326119090317667673915822106846596918013800899458254186 172
UVM_INFO @ 509562603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58070289847037275015658182086032664372926632291310272005890266838784244048503 133
UVM_INFO @ 892382648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 62120490976803829747563519846965637112353683799564753261800731822352721239905 80
UVM_INFO @ 17696763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---