Simulation Results: hmac

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.02 %
  • code
  • 99.32 %
  • assert
  • 97.80 %
  • func
  • 99.95 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.85 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
98.46%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 13.420s 4509.957us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.100s 53.807us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.350s 40.154us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 11.870s 323.680us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 9.840s 585.757us 5 5 100.00
csr_mem_rw_with_rand_reset 19 20 95.00
hmac_csr_mem_rw_with_rand_reset 1182.980s 604799.307us 19 20 95.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.350s 40.154us 20 20 100.00
hmac_csr_aliasing 9.840s 585.757us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 74.720s 21430.265us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 98.280s 8038.683us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 256.350s 6503.880us 30 30 100.00
hmac_test_sha384_vectors 546.080s 14769.784us 75 75 100.00
hmac_test_sha512_vectors 539.170s 15677.416us 75 75 100.00
hmac_test_hmac256_vectors 14.120s 325.186us 50 50 100.00
hmac_test_hmac384_vectors 14.770s 859.046us 60 60 100.00
hmac_test_hmac512_vectors 18.280s 398.527us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 31.970s 1822.518us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1214.550s 23171.312us 10 10 100.00
error 10 10 100.00
hmac_error 107.600s 39756.768us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 119.600s 91051.609us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 13.420s 4509.957us 10 10 100.00
hmac_long_msg 74.720s 21430.265us 10 10 100.00
hmac_back_pressure 98.280s 8038.683us 25 25 100.00
hmac_datapath_stress 1214.550s 23171.312us 10 10 100.00
hmac_burst_wr 31.970s 1822.518us 50 50 100.00
hmac_stress_all 2761.300s 402467.955us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 13.420s 4509.957us 10 10 100.00
hmac_long_msg 74.720s 21430.265us 10 10 100.00
hmac_back_pressure 98.280s 8038.683us 25 25 100.00
hmac_datapath_stress 1214.550s 23171.312us 10 10 100.00
hmac_wipe_secret 119.600s 91051.609us 10 10 100.00
hmac_test_sha256_vectors 256.350s 6503.880us 30 30 100.00
hmac_test_sha384_vectors 546.080s 14769.784us 75 75 100.00
hmac_test_sha512_vectors 539.170s 15677.416us 75 75 100.00
hmac_test_hmac256_vectors 14.120s 325.186us 50 50 100.00
hmac_test_hmac384_vectors 14.770s 859.046us 60 60 100.00
hmac_test_hmac512_vectors 18.280s 398.527us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 13.420s 4509.957us 10 10 100.00
hmac_long_msg 74.720s 21430.265us 10 10 100.00
hmac_back_pressure 98.280s 8038.683us 25 25 100.00
hmac_datapath_stress 1214.550s 23171.312us 10 10 100.00
hmac_burst_wr 31.970s 1822.518us 50 50 100.00
hmac_error 107.600s 39756.768us 10 10 100.00
hmac_wipe_secret 119.600s 91051.609us 10 10 100.00
hmac_test_sha256_vectors 256.350s 6503.880us 30 30 100.00
hmac_test_sha384_vectors 546.080s 14769.784us 75 75 100.00
hmac_test_sha512_vectors 539.170s 15677.416us 75 75 100.00
hmac_test_hmac256_vectors 14.120s 325.186us 50 50 100.00
hmac_test_hmac384_vectors 14.770s 859.046us 60 60 100.00
hmac_test_hmac512_vectors 18.280s 398.527us 75 75 100.00
hmac_stress_all 2761.300s 402467.955us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2761.300s 402467.955us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.980s 46.504us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 0.990s 128.884us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.470s 197.070us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.470s 197.070us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.100s 53.807us 5 5 100.00
hmac_csr_rw 1.350s 40.154us 20 20 100.00
hmac_csr_aliasing 9.840s 585.757us 5 5 100.00
hmac_same_csr_outstanding 3.080s 160.068us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.100s 53.807us 5 5 100.00
hmac_csr_rw 1.350s 40.154us 20 20 100.00
hmac_csr_aliasing 9.840s 585.757us 5 5 100.00
hmac_same_csr_outstanding 3.080s 160.068us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.320s 123.810us 5 5 100.00
hmac_tl_intg_err 4.720s 621.704us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.720s 621.704us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 13.420s 4509.957us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.290s 274.512us 25 25 100.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 657.850s 12792.612us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.540s 86.034us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:454) [hmac_common_vseq] wait timeout occurred! 2 test runs
hmac_csr_mem_rw_with_rand_reset 87470277966238008744696790793250774535938654714989536207018173104677548861655 80
UVM_INFO @ 10040598906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
hmac_stress_all_with_rand_reset 62383037986873374156410751304414762300963234996986280907889210736775292969082 33428
UVM_INFO @ 37572321485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---