Simulation Results

Simulation Results: keymgr

16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.94 %

code
98.90 %

assert
97.72 %

func
91.21 %

line
99.20 %

branch
99.00 %

cond
98.04 %

toggle
98.24 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		99.35%
V2S		99.22%
V3		40.00%

155/155 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				50	50	100.00
	keymgr_smoke	19.300s	1006.790us	50	50	100.00
random				50	50	100.00
	keymgr_random	24.450s	3090.308us	50	50	100.00
csr_hw_reset				5	5	100.00
	keymgr_csr_hw_reset	1.510s	23.802us	5	5	100.00
csr_rw				20	20	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
csr_bit_bash				5	5	100.00
	keymgr_csr_bit_bash	13.010s	886.222us	5	5	100.00
csr_aliasing				5	5	100.00
	keymgr_csr_aliasing	11.690s	1441.277us	5	5	100.00
csr_mem_rw_with_rand_reset				20	20	100.00
	keymgr_csr_mem_rw_with_rand_reset	2.500s	59.032us	20	20	100.00
regwen_csr_and_corresponding_lockable_csr				25	25	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
	keymgr_csr_aliasing	11.690s	1441.277us	5	5	100.00

765/770 passed

99.35 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
cfgen_during_op				49	50	98.00
	keymgr_cfg_regwen	73.010s	21875.470us	49	50	98.00
sideload				200	200	100.00
	keymgr_sideload	31.700s	4782.944us	50	50	100.00
	keymgr_sideload_kmac	35.190s	3865.207us	50	50	100.00
	keymgr_sideload_aes	48.460s	7157.125us	50	50	100.00
	keymgr_sideload_otbn	20.230s	813.001us	50	50	100.00
direct_to_disabled_state				50	50	100.00
	keymgr_direct_to_disabled	19.280s	1024.803us	50	50	100.00
lc_disable				49	50	98.00
	keymgr_lc_disable	27.600s	6481.708us	49	50	98.00
kmac_error_response				50	50	100.00
	keymgr_kmac_rsp_err	5.720s	109.233us	50	50	100.00
invalid_sw_input				49	50	98.00
	keymgr_sw_invalid_input	36.970s	3611.151us	49	50	98.00
invalid_hw_input				50	50	100.00
	keymgr_hwsw_invalid_input	49.310s	6967.612us	50	50	100.00
sync_async_fault_cross				50	50	100.00
	keymgr_sync_async_fault_cross	10.860s	2595.531us	50	50	100.00
stress_all				48	50	96.00
	keymgr_stress_all	279.890s	29048.119us	48	50	96.00
intr_test				50	50	100.00
	keymgr_intr_test	1.260s	11.936us	50	50	100.00
alert_test				50	50	100.00
	keymgr_alert_test	1.290s	17.780us	50	50	100.00
tl_d_oob_addr_access				20	20	100.00
	keymgr_tl_errors	4.480s	144.432us	20	20	100.00
tl_d_illegal_access				20	20	100.00
	keymgr_tl_errors	4.480s	144.432us	20	20	100.00
tl_d_outstanding_access				50	50	100.00
	keymgr_csr_hw_reset	1.510s	23.802us	5	5	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
	keymgr_csr_aliasing	11.690s	1441.277us	5	5	100.00
	keymgr_same_csr_outstanding	3.850s	1427.948us	20	20	100.00
tl_d_partial_access				50	50	100.00
	keymgr_csr_hw_reset	1.510s	23.802us	5	5	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
	keymgr_csr_aliasing	11.690s	1441.277us	5	5	100.00
	keymgr_same_csr_outstanding	3.850s	1427.948us	20	20	100.00

V2S

382/385 passed

99.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
tl_intg_err				25	25	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
	keymgr_tl_intg_err	8.210s	2790.319us	20	20	100.00
shadow_reg_update_error				20	20	100.00
	keymgr_shadow_reg_errors	6.660s	404.704us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	keymgr_shadow_reg_errors	6.660s	404.704us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	keymgr_shadow_reg_errors	6.660s	404.704us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	keymgr_shadow_reg_errors	6.660s	404.704us	20	20	100.00
shadow_reg_update_error_with_csr_rw				20	20	100.00
	keymgr_shadow_reg_errors_with_csr_rw	16.080s	4364.369us	20	20	100.00
prim_count_check				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
prim_fsm_check				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_bus_integrity				20	20	100.00
	keymgr_tl_intg_err	8.210s	2790.319us	20	20	100.00
sec_cm_config_shadow				20	20	100.00
	keymgr_shadow_reg_errors	6.660s	404.704us	20	20	100.00
sec_cm_op_config_regwen				49	50	98.00
	keymgr_cfg_regwen	73.010s	21875.470us	49	50	98.00
sec_cm_reseed_config_regwen				70	70	100.00
	keymgr_random	24.450s	3090.308us	50	50	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
sec_cm_sw_binding_config_regwen				70	70	100.00
	keymgr_random	24.450s	3090.308us	50	50	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
sec_cm_max_key_ver_config_regwen				70	70	100.00
	keymgr_random	24.450s	3090.308us	50	50	100.00
	keymgr_csr_rw	1.780s	26.591us	20	20	100.00
sec_cm_lc_ctrl_intersig_mubi				49	50	98.00
	keymgr_lc_disable	27.600s	6481.708us	49	50	98.00
sec_cm_constants_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	49.310s	6967.612us	50	50	100.00
sec_cm_intersig_consistency				50	50	100.00
	keymgr_hwsw_invalid_input	49.310s	6967.612us	50	50	100.00
sec_cm_hw_key_sw_noaccess				50	50	100.00
	keymgr_random	24.450s	3090.308us	50	50	100.00
sec_cm_output_keys_ctrl_redun				50	50	100.00
	keymgr_sideload_protect	18.690s	4061.020us	50	50	100.00
sec_cm_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_data_fsm_sparse				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_ctrl_fsm_local_esc				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_ctrl_fsm_consistency				49	50	98.00
	keymgr_custom_cm	22.680s	1424.493us	49	50	98.00
sec_cm_ctrl_fsm_global_esc				49	50	98.00
	keymgr_lc_disable	27.600s	6481.708us	49	50	98.00
sec_cm_ctrl_ctr_redun				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_kmac_if_fsm_sparse				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_kmac_if_ctr_redun				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_kmac_if_cmd_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	22.680s	1424.493us	49	50	98.00
sec_cm_kmac_if_done_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	22.680s	1424.493us	49	50	98.00
sec_cm_reseed_ctr_redun				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_side_load_sel_ctrl_consistency				49	50	98.00
	keymgr_custom_cm	22.680s	1424.493us	49	50	98.00
sec_cm_sideload_ctrl_fsm_sparse				5	5	100.00
	keymgr_sec_cm	22.240s	1492.935us	5	5	100.00
sec_cm_ctrl_key_integrity				49	50	98.00
	keymgr_custom_cm	22.680s	1424.493us	49	50	98.00

20/50 passed

40.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				20	50	40.00
	keymgr_stress_all_with_rand_reset	39.050s	5735.143us	20	50	40.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				29 test runs
	keymgr_stress_all_with_rand_reset	98909734214483206507802012671397710970083995962829862050596056202702780627970	118	UVM_INFO @ 115864130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	23157825883215232201372046836790602543265792460559766435981309841893331620244	323	UVM_INFO @ 505796601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	113613349238546213319878281158524067944424387365397143118923767843118451812657	387	UVM_INFO @ 202919652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	39548434500728177686374623718590609550158497151227607195468011656533842756399	483	UVM_INFO @ 638358384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	74284282417445326879229332877946138854711478761085207407624558042245953571434	377	UVM_INFO @ 228158616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	101689079984625747050009695258589884123277993756273658044673094560340778550945	168	UVM_INFO @ 239499329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	98824583317212467875585691748952078535702921573588950181053725996931033725733	97	UVM_INFO @ 106956488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	73388303737120936635723464446021564647691523216532669980556226512152300419831	162	UVM_INFO @ 132976896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	89326404138173485981447754167242090744351073390707857976218073944143028094585	275	UVM_INFO @ 852875917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	40323606683704995771124338587409030585838613516144175880313332721532486785010	770	UVM_INFO @ 1609570695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	106098232138821279120711602290646072245576182925606457641501191428201096781964	428	UVM_INFO @ 476828555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	81846398292007978398989994876974700805601466183775634760432152531275245672169	471	UVM_INFO @ 500919953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	32107455563304057759803207245193787105370237203794992547286693324812179330712	198	UVM_INFO @ 276295830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	87415080495744147142447346946932717401698951856396234977764516042331013305100	214	UVM_INFO @ 966486338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	84934520382735168789445986421417799957887525951013515851779773693544379108499	396	UVM_INFO @ 168305981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	78211735220835383832494513098051455941543611279103015330286965899369767518186	563	UVM_INFO @ 283471133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	46750646915436521817952144009263757967807981615236997192320273620339714542936	538	UVM_INFO @ 198164826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	90276704407070645959247183405232575031372233517963210186677791122525906729480	574	UVM_INFO @ 218820815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	81583281722016480627876293677321278853372937261572148237547103024261025777389	121	UVM_INFO @ 121224835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	65318775286463726340772088823685472316812226416978495220276988736873583007057	751	UVM_INFO @ 492858511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	2223242759476103217100966824680518064529685428040225058250027936069235374025	196	UVM_INFO @ 290922078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	98859279242074766204722994555057154719508392701007349442979261994828288228274	137	UVM_INFO @ 411010865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	21556787295759348172181517497695241450232837335497602689340165129374751921715	292	UVM_INFO @ 172400702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	67159354382895181929911548865437713448020703634126793429310774880508947076101	196	UVM_INFO @ 458633620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	63410731430527496729784275516066790445996644677547518246123853216446518553099	299	UVM_INFO @ 798939599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	99711386124363206482029920132316121783941608312446024476693969178599776240107	158	UVM_INFO @ 105613516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	3658271793048961665532276853683552071033432232411886595680389126767832387004	549	UVM_INFO @ 836295715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	38299956012516547854089227186601866363411572303050730647317137579065256295772	2117	UVM_INFO @ 5735143413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_stress_all_with_rand_reset	11918279611637507262428874778573114285522405089495933413732016847422377293248	106	UVM_INFO @ 150116534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*				3 test runs
	keymgr_sw_invalid_input	106082328703652406511099457524975600293965224166998280254716880233429772150081	414	UVM_INFO @ 53940375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_cfg_regwen	93115616519505106612786621663903709796670643614171852305352915425093526932149	393	UVM_INFO @ 353473953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	keymgr_lc_disable	87516079007632691745418300621552037512940305861009967660769855926521923364029	215	UVM_INFO @ 55939766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[], act_key.key[]} !== keys_a_array[state][cdi][dest] (* [] vs [*]) KMAC key at state StDisabled for Sealing Kmac				1 test run
	keymgr_stress_all	60876285368392940979946773340213140533364107033485150318714908738849679249804	3241	UVM_INFO @ 6500190735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [keymgr_common_vseq] wait timeout occurred!				1 test run
	keymgr_stress_all_with_rand_reset	44529442608483375159643622087384391933694011790931549817166252798301381396714	170	UVM_INFO @ 10200801687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: keymgr_reg_block.fault_status.cmd reset value:				1 test run
	keymgr_custom_cm	84215129946981405199876067726044966009832916003487041974808047094324655297242	304	UVM_INFO @ 192052672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [] vs []) reg name: keymgr_reg_block.sw_share0_output_				1 test run
	keymgr_stress_all	16361064374340072779430595986454571678751054046226778878360991301088550587462	2431	UVM_INFO @ 25880755229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---