Simulation Results: kmac/masked

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.56 %
  • code
  • 93.84 %
  • assert
  • 97.98 %
  • func
  • 97.85 %
  • line
  • 99.25 %
  • branch
  • 97.08 %
  • cond
  • 94.79 %
  • toggle
  • 99.89 %
  • FSM
  • 78.17 %
Validation stages
V1
99.13%
V2
99.87%
V2S
99.56%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 49 50 98.00
kmac_smoke 96.750s 4933.008us 49 50 98.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.490s 27.529us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.560s 120.682us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.670s 1442.088us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 10.090s 1720.500us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.410s 722.003us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.560s 120.682us 20 20 100.00
kmac_csr_aliasing 10.090s 1720.500us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.130s 12.542us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.820s 59.534us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4460.720s 227637.482us 50 50 100.00
burst_write 49 50 98.00
kmac_burst_write 1404.190s 70449.647us 49 50 98.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2582.930s 238842.443us 5 5 100.00
kmac_test_vectors_sha3_256 2277.000s 121991.654us 5 5 100.00
kmac_test_vectors_sha3_384 1850.170s 67327.061us 5 5 100.00
kmac_test_vectors_sha3_512 20.280s 13438.333us 5 5 100.00
kmac_test_vectors_shake_128 2729.580s 641052.344us 5 5 100.00
kmac_test_vectors_shake_256 389.860s 56223.412us 5 5 100.00
kmac_test_vectors_kmac 3.710s 136.979us 5 5 100.00
kmac_test_vectors_kmac_xof 3.870s 649.512us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 437.090s 31194.351us 50 50 100.00
app 50 50 100.00
kmac_app 362.870s 31911.681us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 301.070s 19951.999us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 397.000s 18033.023us 50 50 100.00
error 50 50 100.00
kmac_error 488.200s 73054.858us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 15.940s 2109.916us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 8.330s 503.008us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 37.650s 2191.459us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 24.880s 2949.680us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 65.830s 10388.237us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 38.270s 3196.076us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2838.830s 178212.464us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.230s 45.844us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.290s 69.599us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.420s 305.912us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.420s 305.912us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.490s 27.529us 5 5 100.00
kmac_csr_rw 1.560s 120.682us 20 20 100.00
kmac_csr_aliasing 10.090s 1720.500us 5 5 100.00
kmac_same_csr_outstanding 2.950s 172.556us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.490s 27.529us 5 5 100.00
kmac_csr_rw 1.560s 120.682us 20 20 100.00
kmac_csr_aliasing 10.090s 1720.500us 5 5 100.00
kmac_same_csr_outstanding 2.950s 172.556us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 3.060s 132.055us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 3.060s 132.055us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 3.060s 132.055us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 3.060s 132.055us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
kmac_shadow_reg_errors_with_csr_rw 6.660s 291.365us 20 20 100.00
tl_intg_err 25 25 100.00
kmac_sec_cm 67.070s 18806.379us 5 5 100.00
kmac_tl_intg_err 6.050s 1185.020us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.050s 1185.020us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 38.270s 3196.076us 50 50 100.00
sec_cm_sw_key_key_masking 49 50 98.00
kmac_smoke 96.750s 4933.008us 49 50 98.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 437.090s 31194.351us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 3.060s 132.055us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 67.070s 18806.379us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 67.070s 18806.379us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 67.070s 18806.379us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 49 50 98.00
kmac_smoke 96.750s 4933.008us 49 50 98.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 38.270s 3196.076us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 67.070s 18806.379us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 335.270s 6309.926us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 49 50 98.00
kmac_smoke 96.750s 4933.008us 49 50 98.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
kmac_stress_all_with_rand_reset 250.680s 18225.156us 9 10 90.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 1 test run
kmac_stress_all_with_rand_reset 98431751000790738080785898769772655912650006875059456124412055266022956127654 217
UVM_INFO @ 4818452443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 1 test run
kmac_smoke 103414248337884040611816890325637308478881068271922004363573286566598882071441 77
UVM_INFO @ 156095176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
kmac_burst_write 25109035226677047824056554399590919890128004031127619207123506935076933623431 233
UVM_INFO @ 500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---