Simulation Results: kmac/unmasked

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.70 %
  • code
  • 92.22 %
  • assert
  • 97.90 %
  • func
  • 96.97 %
  • line
  • 97.65 %
  • branch
  • 95.93 %
  • cond
  • 94.79 %
  • toggle
  • 100.00 %
  • FSM
  • 72.73 %
Validation stages
V1
100.00%
V2
98.44%
V2S
99.56%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 79.760s 4471.252us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.540s 39.695us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.570s 260.017us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 23.210s 2951.665us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 8.220s 723.635us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.030s 309.318us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.570s 260.017us 20 20 100.00
kmac_csr_aliasing 8.220s 723.635us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.100s 11.753us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.960s 44.260us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4738.250s 1669875.669us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 815.560s 26358.522us 50 50 100.00
test_vectors 40 40 100.00
kmac_test_vectors_sha3_224 2278.170s 362599.959us 5 5 100.00
kmac_test_vectors_sha3_256 2167.350s 820178.400us 5 5 100.00
kmac_test_vectors_sha3_384 1328.190s 114328.762us 5 5 100.00
kmac_test_vectors_sha3_512 21.680s 4241.816us 5 5 100.00
kmac_test_vectors_shake_128 189.870s 50205.068us 5 5 100.00
kmac_test_vectors_shake_256 1827.120s 76056.451us 5 5 100.00
kmac_test_vectors_kmac 3.480s 419.321us 5 5 100.00
kmac_test_vectors_kmac_xof 3.180s 122.215us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 361.110s 20647.697us 50 50 100.00
app 50 50 100.00
kmac_app 283.890s 17475.870us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 195.510s 10636.991us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 319.770s 74476.022us 50 50 100.00
error 50 50 100.00
kmac_error 414.300s 163859.996us 50 50 100.00
key_error 50 50 100.00
kmac_key_error 12.790s 6725.166us 50 50 100.00
sideload_invalid 38 50 76.00
kmac_sideload_invalid 105.370s 10097.833us 38 50 76.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 38.620s 21057.422us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 47.630s 4047.687us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 66.260s 8992.662us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 34.520s 1326.072us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 2790.890s 146881.358us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.250s 35.512us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.190s 22.425us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.830s 924.340us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.830s 924.340us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.540s 39.695us 5 5 100.00
kmac_csr_rw 1.570s 260.017us 20 20 100.00
kmac_csr_aliasing 8.220s 723.635us 5 5 100.00
kmac_same_csr_outstanding 3.460s 734.253us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.540s 39.695us 5 5 100.00
kmac_csr_rw 1.570s 260.017us 20 20 100.00
kmac_csr_aliasing 8.220s 723.635us 5 5 100.00
kmac_same_csr_outstanding 3.460s 734.253us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 3.060s 521.608us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 3.060s 521.608us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 3.060s 521.608us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 3.060s 521.608us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 5.490s 383.558us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 47.620s 18772.770us 5 5 100.00
kmac_tl_intg_err 6.140s 534.568us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 6.140s 534.568us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 34.520s 1326.072us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 79.760s 4471.252us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 361.110s 20647.697us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 3.060s 521.608us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 47.620s 18772.770us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 47.620s 18772.770us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 47.620s 18772.770us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 79.760s 4471.252us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 34.520s 1326.072us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 47.620s 18772.770us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 247.820s 15625.727us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 79.760s 4471.252us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 159.740s 13894.139us 8 10 80.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) 5 test runs
kmac_sideload_invalid 78153975345253392826327921322124481391087229031489180464078794794951441321344 78
UVM_INFO @ 10058463469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 45684029709759812431241748732145961072368536034900759501678272555006246570267 78
UVM_INFO @ 10012404864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 85362142340108975266592238271234872541116067890340009199392872358272768341958 78
UVM_INFO @ 10037582638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 54710386976150194235069810599630909280916628141793520290529240524630111734170 78
UVM_INFO @ 10018996925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_sideload_invalid 114722343087975715930264277398318979304561528786145276060706274564278496039138 78
UVM_INFO @ 10020364186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
kmac_stress_all_with_rand_reset 53552625879305821932499188817058990973879426818413112276907612864836988552194 99
UVM_INFO @ 5775103501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 28034808203504257698335490176240483930116152252333502952973209611657198448463 323
UVM_INFO @ 4332451984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) 1 test run
kmac_sideload_invalid 104348227434354416478729286387937693905756055328600804729274555237952101067377 80
UVM_INFO @ 10061869038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) 1 test run
kmac_sideload_invalid 10883737263397817896048366020826887165511791021633535879343223121461095012586 83
UVM_INFO @ 10334070412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) 1 test run
kmac_sideload_invalid 76734517739981079454899592069901875302325217090326017375903622158517467496552 79
UVM_INFO @ 10078911942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 51714869142329542611188135072389190974907004626424892463538849913287270893683 351
UVM_INFO @ 211710425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=10) 1 test run
kmac_sideload_invalid 53696623029427016034467295512728971377086303351937964284509206449691026380328 88
UVM_INFO @ 10292338295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) 1 test run
kmac_sideload_invalid 18416248422613688103030182062889255720814375599346034971022508323751027335590 88
UVM_INFO @ 10097832669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) 1 test run
kmac_sideload_invalid 69318469882623290840182065400647579252939406874162142231900150511587343610921 104
UVM_INFO @ 10511052607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) 1 test run
kmac_sideload_invalid 100295538590054790981236416412954660463365298940400430429156403838956762323954 96
UVM_INFO @ 10488222482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---