Simulation Results: lc_ctrl/volatile_unlock_disabled

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.26 %
  • code
  • 86.39 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.28 %
  • branch
  • 94.14 %
  • cond
  • 81.84 %
  • toggle
  • 89.54 %
  • FSM
  • 69.16 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
V3
44.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 6.420s 206.699us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.600s 21.458us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.470s 20.539us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.690s 60.689us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.570s 131.993us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.980s 141.933us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.470s 20.539us 20 20 100.00
lc_ctrl_csr_aliasing 1.570s 131.993us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 9.340s 82.117us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 17.630s 8874.650us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.230s 34.756us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 3.630s 100.008us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_errors 49 50 98.00
lc_ctrl_errors 12.140s 349.967us 49 50 98.00
security_escalation 257 260 98.85
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_prog_failure 3.630s 100.008us 50 50 100.00
lc_ctrl_errors 12.140s 349.967us 49 50 98.00
lc_ctrl_security_escalation 12.300s 6213.687us 50 50 100.00
lc_ctrl_jtag_state_failure 76.480s 3383.297us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.290s 1440.311us 20 20 100.00
lc_ctrl_jtag_errors 68.660s 3733.822us 18 20 90.00
jtag_access 208 210 99.05
lc_ctrl_jtag_smoke 8.880s 1444.489us 20 20 100.00
lc_ctrl_jtag_state_post_trans 27.600s 1051.678us 20 20 100.00
lc_ctrl_jtag_prog_failure 11.290s 1440.311us 20 20 100.00
lc_ctrl_jtag_errors 68.660s 3733.822us 18 20 90.00
lc_ctrl_jtag_access 23.740s 5088.333us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 22.780s 4275.487us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.700s 499.688us 10 10 100.00
lc_ctrl_jtag_csr_rw 4.090s 1015.189us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.150s 7198.948us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 16.920s 4483.316us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.220s 42.178us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.220s 470.320us 10 10 100.00
lc_ctrl_jtag_alert_test 2.010s 131.572us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 10.870s 1422.099us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.430s 24.013us 50 50 100.00
stress_all 49 50 98.00
lc_ctrl_stress_all 677.540s 55070.169us 49 50 98.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.680s 557.839us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.870s 447.134us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.870s 447.134us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.600s 21.458us 5 5 100.00
lc_ctrl_csr_rw 1.470s 20.539us 20 20 100.00
lc_ctrl_csr_aliasing 1.570s 131.993us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.280s 81.769us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.600s 21.458us 5 5 100.00
lc_ctrl_csr_rw 1.470s 20.539us 20 20 100.00
lc_ctrl_csr_aliasing 1.570s 131.993us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.280s 81.769us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
lc_ctrl_tl_intg_err 4.420s 498.831us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.420s 498.831us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 17.630s 8874.650us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 13.400s 379.031us 50 50 100.00
lc_ctrl_sec_cm 10.350s 995.631us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 12.300s 6213.687us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 9.340s 82.117us 50 50 100.00
lc_ctrl_jtag_state_post_trans 27.600s 1051.678us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 13.850s 411.751us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 13.850s 411.751us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 18.810s 858.779us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.020s 607.794us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 13.020s 607.794us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 22 50 44.00
lc_ctrl_stress_all_with_rand_reset 191.810s 14024.128us 22 50 44.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 24 test runs
lc_ctrl_stress_all_with_rand_reset 79193215805045513962735207384926290086902086083228896848753615469465953129867 4705
UVM_INFO @ 1157477164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 113707238335445615341136687586459355269195533980841280557536938483447389979565 5559
UVM_INFO @ 13194776691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 76393882978122138587542962957999973369659880152128838017509372120844037918270 157
UVM_INFO @ 1415459481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92772835088518204272360495867343009720235732086470488626898659875968016334132 1532
UVM_INFO @ 2418003631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30096693882163331980487869197738318488922441261915391020262336843174293851014 3014
UVM_INFO @ 8309715118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 86038684157850825212675123199071043955784304852512344266423333272715247053928 6063
UVM_INFO @ 1870964845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 73385469433681868543370176447805061812460137341531860178516100153887333485669 11079
UVM_INFO @ 6631375376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 87736742579706907795843350760873159476158200189610349715208270546887617414406 264
UVM_INFO @ 820508557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95657494700821258511120168085813398063199002867021298551064673930694107808124 965
UVM_INFO @ 1027700141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 56282629425044308237054032058545230539717188359294635694820843929751449191267 1090
UVM_INFO @ 5619635240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 3550562977132367305785691694996906941796092805358413598713962261754836210303 159
UVM_INFO @ 1019664564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 108296028336442122200092979538842066406177356990810655495783288535134638441332 7744
UVM_INFO @ 5406918141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 20661223947513048326578249368205394509259654342578388676581279341023848200771 892
UVM_INFO @ 4207842578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68812257181992302770852263957769584567016534464666448921023247068511080325714 155
UVM_INFO @ 1538863631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2388370788930611281115307662058058894507459909799736749371266498658363791360 151
UVM_INFO @ 426760558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 29027430744435973372193838592946960566420483947464619045042223933722108101585 4310
UVM_INFO @ 3452346618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 65973090030839611649763832122789165429825742935611078126346284036786999977938 1495
UVM_INFO @ 5757217423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 27025593917849511171717568473193768429003144685227577065746080901547431576463 151
UVM_INFO @ 105234734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 19285976672140914770438795832737898260091156009907897780419560076769590982063 5123
UVM_INFO @ 1838150074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50886953022862934872961741128897100708032928637289864218699688816330077677082 3928
UVM_INFO @ 6791710086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 41188455681756651418395617435262465989362406360846645159048567430544510618185 151
UVM_INFO @ 111697766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 39525052302643851218873093904997531187551186191795987848380311025622307267561 803
UVM_INFO @ 2751531195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13911450934084518433212099431276995960705053029756217042764805328540019750890 5842
UVM_INFO @ 22876443364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 66880588509370226076077301016375247645408378810827243293019485453053981947554 9307
UVM_INFO @ 1836631013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 6 test runs
lc_ctrl_jtag_errors 33378416461608246171406733093485922572461384414851711996726069175494635374501 790
UVM_INFO @ 1149993861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 70245865877937308368478425257577964399373458096122400727375923437619952827738 3362
UVM_INFO @ 1514415617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 35963956787886583075747096682653533226750908250034708438906117805556939306973 4168
UVM_INFO @ 332770332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74161020075557489587296568924435310064628846309273012387207923780136494171783 2636
UVM_INFO @ 5955321410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 96459990501842750268846155205687862988136191651041962924518013728519817046296 786
UVM_INFO @ 59257029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 85748090230971218754455712930542706688357344167995979890277647093407170576329 195
UVM_INFO @ 36984671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 45994563640120553989853259674615996113598942386319718777587852243561734540173 23052
UVM_INFO @ 14024128165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1149) [lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
lc_ctrl_stress_all_with_rand_reset 908653694035570642339538028901580107066093920274837702989800727508561092279 2060
UVM_INFO @ 784844207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---