Simulation Results: lc_ctrl/volatile_unlock_enabled

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.32 %
  • code
  • 86.58 %
  • assert
  • 94.13 %
  • func
  • 96.26 %
  • line
  • 97.26 %
  • branch
  • 94.09 %
  • cond
  • 81.90 %
  • toggle
  • 89.54 %
  • FSM
  • 70.09 %
Validation stages
V1
100.00%
V2
99.18%
V2S
100.00%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
lc_ctrl_smoke 4.640s 88.615us 50 50 100.00
csr_hw_reset 5 5 100.00
lc_ctrl_csr_hw_reset 1.310s 28.022us 5 5 100.00
csr_rw 20 20 100.00
lc_ctrl_csr_rw 1.240s 17.569us 20 20 100.00
csr_bit_bash 5 5 100.00
lc_ctrl_csr_bit_bash 1.590s 94.168us 5 5 100.00
csr_aliasing 5 5 100.00
lc_ctrl_csr_aliasing 1.640s 54.922us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.730s 54.077us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
lc_ctrl_csr_rw 1.240s 17.569us 20 20 100.00
lc_ctrl_csr_aliasing 1.640s 54.922us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 50 50 100.00
lc_ctrl_state_post_trans 7.480s 88.386us 50 50 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 14.360s 300.028us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 1.070s 14.801us 10 10 100.00
lc_prog_failure 50 50 100.00
lc_ctrl_prog_failure 3.390s 616.807us 50 50 100.00
lc_state_failure 50 50 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_errors 48 50 96.00
lc_ctrl_errors 18.450s 798.072us 48 50 96.00
security_escalation 257 260 98.85
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_prog_failure 3.390s 616.807us 50 50 100.00
lc_ctrl_errors 18.450s 798.072us 48 50 96.00
lc_ctrl_security_escalation 10.810s 634.377us 50 50 100.00
lc_ctrl_jtag_state_failure 74.430s 5599.459us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.670s 793.786us 20 20 100.00
lc_ctrl_jtag_errors 66.870s 14405.252us 19 20 95.00
jtag_access 209 210 99.52
lc_ctrl_jtag_smoke 10.650s 537.274us 20 20 100.00
lc_ctrl_jtag_state_post_trans 21.320s 2169.761us 20 20 100.00
lc_ctrl_jtag_prog_failure 13.670s 793.786us 20 20 100.00
lc_ctrl_jtag_errors 66.870s 14405.252us 19 20 95.00
lc_ctrl_jtag_access 16.110s 914.771us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 25.670s 6660.228us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 4.450s 248.683us 10 10 100.00
lc_ctrl_jtag_csr_rw 2.070s 175.080us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 27.860s 1864.377us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 13.090s 2921.362us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 1.620s 24.166us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.280s 204.979us 10 10 100.00
lc_ctrl_jtag_alert_test 1.830s 370.373us 10 10 100.00
jtag_priority 10 10 100.00
lc_ctrl_jtag_priority 11.670s 1548.032us 10 10 100.00
lc_ctrl_volatile_unlock 50 50 100.00
lc_ctrl_volatile_unlock_smoke 1.500s 27.516us 50 50 100.00
stress_all 47 50 94.00
lc_ctrl_stress_all 444.700s 16428.075us 47 50 94.00
alert_test 50 50 100.00
lc_ctrl_alert_test 1.580s 43.223us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
lc_ctrl_tl_errors 3.920s 141.031us 20 20 100.00
tl_d_illegal_access 20 20 100.00
lc_ctrl_tl_errors 3.920s 141.031us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 28.022us 5 5 100.00
lc_ctrl_csr_rw 1.240s 17.569us 20 20 100.00
lc_ctrl_csr_aliasing 1.640s 54.922us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.280s 193.040us 20 20 100.00
tl_d_partial_access 50 50 100.00
lc_ctrl_csr_hw_reset 1.310s 28.022us 5 5 100.00
lc_ctrl_csr_rw 1.240s 17.569us 20 20 100.00
lc_ctrl_csr_aliasing 1.640s 54.922us 5 5 100.00
lc_ctrl_same_csr_outstanding 2.280s 193.040us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
lc_ctrl_tl_intg_err 4.150s 662.309us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
lc_ctrl_tl_intg_err 4.150s 662.309us 20 20 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 14.360s 300.028us 10 10 100.00
sec_cm_manuf_state_sparse 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_transition_ctr_sparse 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_state_config_sparse 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_main_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_kmac_fsm_sparse 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_main_fsm_local_esc 55 55 100.00
lc_ctrl_state_failure 11.580s 1579.057us 50 50 100.00
lc_ctrl_sec_cm 9.300s 346.354us 5 5 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
lc_ctrl_security_escalation 10.810s 634.377us 50 50 100.00
sec_cm_main_ctrl_flow_consistency 70 70 100.00
lc_ctrl_state_post_trans 7.480s 88.386us 50 50 100.00
lc_ctrl_jtag_state_post_trans 21.320s 2169.761us 20 20 100.00
sec_cm_intersig_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.450s 3757.516us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
lc_ctrl_sec_mubi 12.450s 3757.516us 50 50 100.00
sec_cm_token_digest 50 50 100.00
lc_ctrl_sec_token_digest 14.320s 2314.782us 50 50 100.00
sec_cm_token_mux_ctrl_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.110s 547.042us 50 50 100.00
sec_cm_token_valid_mux_redun 50 50 100.00
lc_ctrl_sec_token_mux 11.110s 547.042us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 21 50 42.00
lc_ctrl_stress_all_with_rand_reset 168.500s 22681.549us 21 50 42.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 24 test runs
lc_ctrl_stress_all_with_rand_reset 19092630742151338194462406471629623903741367264061766481631051318214721942697 1306
UVM_INFO @ 8232656075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104560201611860587656907393577680671242163926374311157174388489994989585985256 151
UVM_INFO @ 520946399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 54544816209291279527570729738020293364956196183485300475194301364496261578754 5431
UVM_INFO @ 2007160210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 30170382411337729222587665279865978669018916776020207663313349255275243906864 14170
UVM_INFO @ 9220849664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 100164127527201200006751341798759687919272096492042452836008906990469608896785 8320
UVM_INFO @ 6672485968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 48814250421906961130584689734297354103281464840246278409468495852844774826146 164
UVM_INFO @ 944808555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 74728026252917236053803834553153038691146979268046249552022404676878866957194 206
UVM_INFO @ 1002171365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 75180828724871933886424430817599248861505490347184437489260635084907919608465 421
UVM_INFO @ 454567533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35573985809411785048885810159882384065921190822306873029206411115410018084743 7953
UVM_INFO @ 8046238933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 35177479765068068787442885629493418094491307708845740600248424079232155977762 8725
UVM_INFO @ 1607412619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 38495243616980489056003251684830361222779723237616922958790694318247974712804 5084
UVM_INFO @ 10630402590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 71850083105250341738225246422890016685611036646435564906544733005066634001183 3900
UVM_INFO @ 5037439814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 92520217654878441690651149778792772983603364720798170636767898211813365670140 300
UVM_INFO @ 511251973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 95935200488422536007773286565700891974879074434050620877382392069995128412948 150
UVM_INFO @ 208319680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 107013377100430417536796116262347652920037079579509934345416197959869845234759 1263
UVM_INFO @ 3883605527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 47507706004867535302816616340455998905200919187311618313836798797685218713541 1948
UVM_INFO @ 2865388058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 37344656749386063765121305787696911079744742184171194802876650715506034370084 7726
UVM_INFO @ 5617934123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 46379370535943356776338210672214320735295506352939453567171661548828309833321 814
UVM_INFO @ 1737830490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 13073339846481121962869516332301770813645249685280943712317918848999244116732 10822
UVM_INFO @ 5414733549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 51291704909914373103230518364071707499429042735563720611087321916058574928473 1151
UVM_INFO @ 4152598848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 97954210006653509073313433821213952851808873541089701377621704258262463779783 8742
UVM_INFO @ 13345542806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 90445941725295256174196552646653708721790020941882214166753305411259574249306 23223
UVM_INFO @ 22094491150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 68923515248542781331493001645938893102217999708258153493947734043573192420438 268
UVM_INFO @ 2160897655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 2250161995356063004324629781140204908462608902158906662283952153061697657287 6361
UVM_INFO @ 10127187425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 6 test runs
lc_ctrl_errors 67516100504599530040443465841967268205803741818602241842681205302343856801942 2172
UVM_INFO @ 140905725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 82644979829013520756018294019238979062702308935494785317636436799520433225565 3686
UVM_INFO @ 936708004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 3822100258814229521510534745499638349670700436913669224281930805367194437662 1310
UVM_INFO @ 1094262317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 30495443100684162331471640520753881281207627831596496961513924209896920318963 7006
UVM_INFO @ 4719547043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_errors 105461510730592254860420199751303014745527447290396258210058794080466630647520 2352
UVM_INFO @ 1623907844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 69609071279214613832973833851649659087013264842728946130191490133077190280976 3396
UVM_INFO @ 5174722041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:912) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 3 test runs
lc_ctrl_stress_all_with_rand_reset 5809459618200660833999107164970036019815786896846773959370063782000463517593 426
UVM_INFO @ 1709618153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 58080438106781150032216811554631297577598500270217524533580840802491467228197 5937
UVM_INFO @ 3697120119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 43884469805933174569316896829039519580975604319038242535673531271269747850396 3976
UVM_INFO @ 8614016210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (lc_ctrl_scoreboard.sv:248) [scoreboard] Check failed cfg.lc_ctrl_vif.lc_escalate_en_o == exp_o.lc_escalate_en_o (* [*] vs * [*]) Called from line: *, LC_St DecLcStTestLocked* 1 test run
lc_ctrl_stress_all_with_rand_reset 28887636999877523247786285705980851524559484997436365857661732901338704998710 2834
UVM_INFO @ 2010026599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [lc_ctrl_common_vseq] wait timeout occurred! 1 test run
lc_ctrl_stress_all_with_rand_reset 3089543696619481657743889049833906992743529271951131772332927838325202587497 7923
UVM_INFO @ 15203751623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---