Simulation Results: otbn

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 98.06 %
  • code
  • 96.82 %
  • assert
  • 97.37 %
  • func
  • 100.00 %
  • block
  • 99.53 %
  • line
  • 99.64 %
  • branch
  • 94.10 %
  • toggle
  • 93.53 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.28%
V2S
98.23%
V3
40.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 34.000s 42.215us 1 1 100.00
single_binary 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
csr_hw_reset 5 5 100.00
otbn_csr_hw_reset 34.000s 74.744us 5 5 100.00
csr_rw 20 20 100.00
otbn_csr_rw 34.000s 15.238us 20 20 100.00
csr_bit_bash 5 5 100.00
otbn_csr_bit_bash 38.000s 272.051us 5 5 100.00
csr_aliasing 5 5 100.00
otbn_csr_aliasing 34.000s 15.717us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 444.523us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otbn_csr_rw 34.000s 15.238us 20 20 100.00
otbn_csr_aliasing 34.000s 15.717us 5 5 100.00
mem_walk 5 5 100.00
otbn_mem_walk 126.000s 10338.035us 5 5 100.00
mem_partial_access 5 5 100.00
otbn_mem_partial_access 53.000s 346.386us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 50.000s 298.999us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 86.000s 256.098us 1 1 100.00
back_to_back 10 10 100.00
otbn_multi 295.000s 1301.832us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 1022.000s 3283.179us 10 10 100.00
lc_escalation 59 60 98.33
otbn_escalate 2356.000s 10016.415us 59 60 98.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 29.000s 182.546us 5 5 100.00
sw_errs_fatal_chk 9 10 90.00
otbn_sw_errs_fatal_chk 34.000s 214.004us 9 10 90.00
alert_test 50 50 100.00
otbn_alert_test 35.000s 37.540us 50 50 100.00
intr_test 50 50 100.00
otbn_intr_test 34.000s 122.448us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otbn_tl_errors 33.000s 75.697us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otbn_tl_errors 33.000s 75.697us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otbn_csr_hw_reset 34.000s 74.744us 5 5 100.00
otbn_csr_rw 34.000s 15.238us 20 20 100.00
otbn_csr_aliasing 34.000s 15.717us 5 5 100.00
otbn_same_csr_outstanding 33.000s 88.311us 20 20 100.00
tl_d_partial_access 50 50 100.00
otbn_csr_hw_reset 34.000s 74.744us 5 5 100.00
otbn_csr_rw 34.000s 15.238us 20 20 100.00
otbn_csr_aliasing 34.000s 15.717us 5 5 100.00
otbn_same_csr_outstanding 33.000s 88.311us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 41.000s 69.080us 10 10 100.00
otbn_dmem_err 30.000s 85.758us 15 15 100.00
internal_integrity 17 17 100.00
otbn_alu_bignum_mod_err 42.000s 159.471us 5 5 100.00
otbn_controller_ispr_rdata_err 31.000s 55.829us 5 5 100.00
otbn_mac_bignum_acc_err 30.000s 17.835us 5 5 100.00
otbn_urnd_err 28.000s 18.191us 2 2 100.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 28.000s 24.023us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 29.000s 70.903us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 30.000s 48.895us 10 10 100.00
tl_intg_err 25 25 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
otbn_tl_intg_err 46.000s 452.688us 20 20 100.00
passthru_mem_tl_intg_err 18 20 90.00
otbn_passthru_mem_tl_intg_err 80.000s 3314.447us 18 20 90.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 34.000s 42.215us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 30.000s 85.758us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 41.000s 69.080us 10 10 100.00
sec_cm_bus_integrity 20 20 100.00
otbn_tl_intg_err 46.000s 452.688us 20 20 100.00
sec_cm_controller_fsm_global_esc 59 60 98.33
otbn_escalate 2356.000s 10016.415us 59 60 98.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 41.000s 69.080us 10 10 100.00
otbn_dmem_err 30.000s 85.758us 15 15 100.00
otbn_zero_state_err_urnd 29.000s 182.546us 5 5 100.00
otbn_illegal_mem_acc 28.000s 24.023us 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 41.000s 69.080us 10 10 100.00
otbn_dmem_err 30.000s 85.758us 15 15 100.00
otbn_zero_state_err_urnd 29.000s 182.546us 5 5 100.00
otbn_illegal_mem_acc 28.000s 24.023us 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 59 60 98.33
otbn_escalate 2356.000s 10016.415us 59 60 98.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 41.000s 69.080us 10 10 100.00
otbn_dmem_err 30.000s 85.758us 15 15 100.00
otbn_zero_state_err_urnd 29.000s 182.546us 5 5 100.00
otbn_illegal_mem_acc 28.000s 24.023us 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_ctrl_redun 11 12 91.67
otbn_ctrl_redun 29.000s 10.499us 11 12 91.67
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 28.000s 37.061us 5 5 100.00
sec_cm_rnd_bus_consistency 4 5 80.00
otbn_rnd_sec_cm 425.000s 2074.149us 4 5 80.00
sec_cm_rnd_rng_digest 4 5 80.00
otbn_rnd_sec_cm 425.000s 2074.149us 4 5 80.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 31.000s 29.997us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 34.000s 105.643us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
sec_cm_loop_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 30.000s 35.017us 5 5 100.00
sec_cm_call_stack_addr_integrity 5 5 100.00
otbn_stack_addr_integ_chk 30.000s 35.017us 5 5 100.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 29.000s 10.399us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 295.000s 1301.832us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 30.000s 31.314us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 59.000s 228.733us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 302.000s 3172.834us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 4 10 40.00
otbn_stress_all_with_rand_reset 709.000s 1872.825us 4 10 40.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 32.000s 75.074us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
otbn_stress_all_with_rand_reset 62632263522483721900708054097787141148589002387843891319724886596894441894371 601
UVM_INFO @ 1872824829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 107936288021402714743909014353131841391915717102332029864854775595397761956597 166
UVM_INFO @ 108444024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 90022750886718445229231305570422298501422021304620980814592762292692845862926 658
UVM_INFO @ 4071089860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 34214582502887133486059381932182437667282432642060100410540504216275290526426 168
UVM_INFO @ 135928442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 36857192956460676709883239970597135634460402951030430810916653942701469519126 292
UVM_INFO @ 4199320807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 3 test runs
otbn_rnd_sec_cm 54865651650399489797046920430502358253187396455553835105697191098407422297549 139
UVM_INFO @ 75691938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 98248472146544836846545683340489821675324157161221394736868957657280484772390 86
UVM_INFO @ 3111647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_passthru_mem_tl_intg_err 14876747719337836374928216700256509463031352228964760161732520396169261967220 86
UVM_INFO @ 1030834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) 1 test run
otbn_stress_all_with_rand_reset 115373008416184712856220846165705850240467250531359312280608483092672246984770 306
UVM_INFO @ 971315729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_sw_errs_fatal_chk 113840945752748340179814736737962363602201187362897205841995992339084791367732 112
UVM_INFO @ 168457871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:486) [otbn_escalate_vseq] Timed out waiting for OTBN run to complete 1 test run
otbn_escalate 112816882511582331783411937526526101346726411455372861937311499477854413096449 119
UVM_INFO @ 10016415021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1028) virtual_sequencer [otbn_rf_bignum_intg_err_vseq] expect alert:fatal to fire 1 test run
otbn_rf_bignum_intg_err 68599421751876896606122893437620925096329219534735110465709942799878558575179 110
UVM_INFO @ 559195902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_controller.sv,703): Assertion NoStallOnBranch has failed 1 test run
otbn_ctrl_redun 37694578942920185448174527614005065644417211386249753921131461643641312223433 108
UVM_ERROR @ 68876768 ps: (otbn_controller.sv:703) [ASSERT FAILED] NoStallOnBranch
UVM_INFO @ 68876768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---