Simulation Results: otp_ctrl

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.22 %
  • code
  • 86.25 %
  • assert
  • 94.75 %
  • func
  • 92.67 %
  • line
  • 90.43 %
  • branch
  • 86.85 %
  • cond
  • 94.10 %
  • toggle
  • 95.82 %
  • FSM
  • 64.06 %
Validation stages
V1
94.83%
V2
96.37%
V2S
95.23%
V3
31.68%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.940s 113.058us 1 1 100.00
smoke 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
csr_hw_reset 5 5 100.00
otp_ctrl_csr_hw_reset 3.080s 1641.925us 5 5 100.00
csr_rw 20 20 100.00
otp_ctrl_csr_rw 1.950s 150.542us 20 20 100.00
csr_bit_bash 5 5 100.00
otp_ctrl_csr_bit_bash 5.710s 2001.525us 5 5 100.00
csr_aliasing 5 5 100.00
otp_ctrl_csr_aliasing 4.350s 241.815us 5 5 100.00
csr_mem_rw_with_rand_reset 14 20 70.00
otp_ctrl_csr_mem_rw_with_rand_reset 56.430s 10046.760us 14 20 70.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
otp_ctrl_csr_rw 1.950s 150.542us 20 20 100.00
otp_ctrl_csr_aliasing 4.350s 241.815us 5 5 100.00
mem_walk 5 5 100.00
otp_ctrl_mem_walk 1.870s 152.514us 5 5 100.00
mem_partial_access 5 5 100.00
otp_ctrl_mem_partial_access 1.750s 556.936us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.180s 1231.254us 1 1 100.00
init_fail 300 300 100.00
otp_ctrl_init_fail 6.220s 2643.317us 300 300 100.00
partition_check 43 60 71.67
otp_ctrl_background_chks 46.970s 24496.877us 10 10 100.00
otp_ctrl_check_fail 21.300s 3577.886us 33 50 66.00
regwen_during_otp_init 50 50 100.00
otp_ctrl_regwen 10.250s 1318.831us 50 50 100.00
partition_lock 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
interface_key_check 50 50 100.00
otp_ctrl_parallel_key_req 41.380s 20186.730us 50 50 100.00
lc_interactions 249 250 99.60
otp_ctrl_parallel_lc_req 24.380s 10715.364us 50 50 100.00
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_dai_errors 48 50 96.00
otp_ctrl_dai_errs 35.080s 25446.616us 48 50 96.00
otp_macro_errors 31 50 62.00
otp_ctrl_macro_errs 47.630s 36291.589us 31 50 62.00
test_access 50 50 100.00
otp_ctrl_test_access 47.660s 12170.478us 50 50 100.00
stress_all 48 50 96.00
otp_ctrl_stress_all 240.700s 142443.326us 48 50 96.00
intr_test 50 50 100.00
otp_ctrl_intr_test 2.350s 558.927us 50 50 100.00
alert_test 50 50 100.00
otp_ctrl_alert_test 2.450s 802.097us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
otp_ctrl_tl_errors 6.000s 2466.105us 20 20 100.00
tl_d_illegal_access 20 20 100.00
otp_ctrl_tl_errors 6.000s 2466.105us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
otp_ctrl_csr_hw_reset 3.080s 1641.925us 5 5 100.00
otp_ctrl_csr_rw 1.950s 150.542us 20 20 100.00
otp_ctrl_csr_aliasing 4.350s 241.815us 5 5 100.00
otp_ctrl_same_csr_outstanding 5.080s 2003.029us 20 20 100.00
tl_d_partial_access 50 50 100.00
otp_ctrl_csr_hw_reset 3.080s 1641.925us 5 5 100.00
otp_ctrl_csr_rw 1.950s 150.542us 20 20 100.00
otp_ctrl_csr_aliasing 4.350s 241.815us 5 5 100.00
otp_ctrl_same_csr_outstanding 5.080s 2003.029us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
tl_intg_err 25 25 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
otp_ctrl_tl_intg_err 18.750s 20004.486us 20 20 100.00
prim_count_check 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
prim_fsm_check 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
otp_ctrl_tl_intg_err 18.750s 20004.486us 20 20 100.00
sec_cm_secret_mem_scramble 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
sec_cm_part_mem_digest 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
sec_cm_dai_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_kdi_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_lci_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_part_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_scrmbl_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_timer_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_dai_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_kdi_seed_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_kdi_entropy_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_lci_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_part_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_scrmbl_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_timer_integ_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_timer_cnsty_ctr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_timer_lfsr_redun 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_dai_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_lci_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
sec_cm_kdi_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
sec_cm_part_fsm_local_esc 230 250 92.00
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_ctrl_macro_errs 47.630s 36291.589us 31 50 62.00
sec_cm_scrmbl_fsm_local_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
sec_cm_timer_fsm_local_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_dai_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_lci_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
sec_cm_kdi_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
sec_cm_part_fsm_global_esc 230 250 92.00
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_ctrl_macro_errs 47.630s 36291.589us 31 50 62.00
sec_cm_scrmbl_fsm_global_esc 199 200 99.50
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
sec_cm_timer_fsm_global_esc 204 205 99.51
otp_ctrl_parallel_lc_esc 56.670s 10001.053us 199 200 99.50
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_part_data_reg_integrity 300 300 100.00
otp_ctrl_init_fail 6.220s 2643.317us 300 300 100.00
sec_cm_part_data_reg_bkgn_chk 33 50 66.00
otp_ctrl_check_fail 21.300s 3577.886us 33 50 66.00
sec_cm_part_mem_regren 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
sec_cm_part_mem_sw_unreadable 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
sec_cm_part_mem_sw_unwritable 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
sec_cm_lc_part_mem_sw_noaccess 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
sec_cm_access_ctrl_mubi 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
sec_cm_token_valid_ctrl_mubi 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
otp_ctrl_dai_lock 159.910s 26555.127us 50 50 100.00
sec_cm_test_bus_lc_gated 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 5 5 100.00
otp_ctrl_sec_cm 175.820s 37322.648us 5 5 100.00
sec_cm_direct_access_config_regwen 50 50 100.00
otp_ctrl_regwen 10.250s 1318.831us 50 50 100.00
sec_cm_check_trigger_config_regwen 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
sec_cm_check_config_regwen 50 50 100.00
otp_ctrl_smoke 13.250s 7428.015us 50 50 100.00
sec_cm_macro_mem_integrity 31 50 62.00
otp_ctrl_macro_errs 47.630s 36291.589us 31 50 62.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.970s 3106.139us 1 1 100.00
stress_all_with_rand_reset 31 100 31.00
otp_ctrl_stress_all_with_rand_reset 159.350s 25199.912us 31 100 31.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 55 test runs
otp_ctrl_macro_errs 66735772617017505521322439801894918426893035822096617883974529924617033445982 5092
UVM_INFO @ 1137627736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 65522112672299801741512688565669141983901625271645765104492028736190489620661 4343
UVM_INFO @ 414786703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85205168170537625080114773208476756388093005525363123943006804743833741329053 19181
UVM_INFO @ 59983716047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 23361212524380917265397174433815552209161131023280347854415394213515680897545 491
UVM_INFO @ 77938530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 95027439388936975593448787179618400045462593467480180617091785806156745136608 355
UVM_INFO @ 178982407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 57082500948137409550263504245607054026289245418644669931268936959985212005888 52467
UVM_INFO @ 24234039761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 39984232343458788654604942287828732520856769631605343896017927601515156388759 913
UVM_INFO @ 110761608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 89545936589851377164896029764175106623717326905040599847878251042033367578673 1715
UVM_INFO @ 134308914 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 104896209639728625077235245471714915986728581792531536950680954484423393509841 7398
UVM_INFO @ 5914908531 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2185378832651444344547091690126797065323850703917664963224690357222089150232 10462
UVM_INFO @ 2485003159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 6989512724910253538254680928161884155143110476401972472012876977758005116587 1111
UVM_INFO @ 81652039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80864686697551905293229395737662045563886740551562143472589938061132778964623 1910
UVM_INFO @ 373484732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 26411065746800775359837210969118087870251971018485547939412461360421276898411 8427
UVM_INFO @ 3577886394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 41632107181969020434252659713160899249217267234545829680849500753239879097707 3811
UVM_INFO @ 296064048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 113999844143797795457780579050070502283147864689650374830958037953939834691981 2866
UVM_INFO @ 399567964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 112972945873244280550926471893685740019825735187261324644598307229019888923274 1407
UVM_INFO @ 3644202455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91174534980860842708618986909062405530684276654482484581183935201379767898324 1824
UVM_INFO @ 1639127106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_dai_errs 92133659644327665888585866816282403230424310102638540261200651139541099131373 847
UVM_INFO @ 190332112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42698987066893926252022295880444279742335762215364718627360836941630744671457 883
UVM_INFO @ 834286498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 29786376932724087594659596066299373552438938961330095472390442294942486917837 1291
UVM_INFO @ 283644793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 30986131303972028755543274509912888423519820788841995522816138692204593510472 1219
UVM_INFO @ 146241581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 23663521005784483881288671250443566624588760173301650966421502993936644565351 7567
UVM_INFO @ 1913582206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 61057716902505232752945868616387519170626863090500087389744576809652725068503 2618
UVM_INFO @ 2530160827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 41463181351451803550124888787717007593995471322823711630800644526664304573447 16662
UVM_INFO @ 1186375056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 49209699570543735415831754923973597472867595944513333655870800372608166846368 10226
UVM_INFO @ 5377567824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54460210818680087163710627801845399627319706056894210574379345910630191692900 4815
UVM_INFO @ 203907251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 27879928778015641338264566618287965015789344112164269058678989523437612711581 4171
UVM_INFO @ 637255083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65885070047667474173149769411865384817191240464651187233230637350746794774857 281
UVM_INFO @ 200702422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 55423143775332407402551679273317332919876584521789609301485410143184855330682 3812
UVM_INFO @ 938988108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 27384006560479977051126933465674941578469817052917113985969871197465594573927 751
UVM_INFO @ 1374586077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 99504150208706994276568324695580357007929171195348524243275569320923604138694 72139
UVM_INFO @ 53715846848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 63191691045893404089198595173347636721832891018724939899508354307973795808323 1805
UVM_INFO @ 202041228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 10460940762776704513052079553496740860371190605202887041211663260810887098709 557
UVM_INFO @ 74514344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 54332232354121776375423248421063205465847298039170555823800331985418684356108 1405
UVM_INFO @ 274850697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 82070950576742948373550630236596488061575133977312517791556541210535377775367 5490
UVM_INFO @ 2090459845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 107258467218755958133854196099291218635497363887540258376901314336569943896463 3516
UVM_INFO @ 238525129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 76704748220284398545718981812257251313851795263451688063536403873714934061875 4718
UVM_INFO @ 381253611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2622213775783267237205218487046222568366243079401185224713189678131606157332 147
UVM_INFO @ 31643753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 17852650067682396480363582545437610404324923653318942277672745397401149990105 23823
UVM_INFO @ 12833775859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 44818726692304212627355344660268979487560146940789965906962655519328441168789 3755
UVM_INFO @ 901606028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 95218007166478827773908733322826898721710299116412085096291735267484208780986 1666
UVM_INFO @ 84662948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 22999279114001596512237183340283221721464141571806643582700668752255403277828 6121
UVM_INFO @ 701313830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2672336523912339722865008262333506319830645267944341289808309229870857914270 26373
UVM_INFO @ 15371694481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 28216111168236444497683769653449338606112389620610788544122986372468211336672 795
UVM_INFO @ 53672808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 61580125320783488726053520757273424024567238485725343344762843628084809974736 2951
UVM_INFO @ 122549012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 94741763933560243050659562520667321993676918407063406584899519601132405788892 7761
UVM_INFO @ 463772625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 105730011927065066196959138479663432184334167481894622554288590335666142375135 11857
UVM_INFO @ 1133844294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 74359646496862946043435280920323420387385754743785092460824508385241635474281 121
UVM_INFO @ 88527367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 1325498925321601202666443910593220570421705341217218146488624097146030769623 16478
UVM_INFO @ 1278566330 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_check_fail 25499862049705343343009093283588483079944825890963551106731015529814410811123 8783
UVM_INFO @ 380766652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 53283199533251058297654866263070235454820484446741620622109757795681465527811 8566
UVM_INFO @ 9367657342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73644705039056173356009014217941910902734289493829988909420482219534561992249 3381
UVM_INFO @ 2471710533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 28651879025876737016265030414157258614094568655188115099633766907580800725105 11851
UVM_INFO @ 968337992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 454668040403956145780311902150334574260725153843959250473505909729284611072 403
UVM_INFO @ 230575015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 101865277413560287458814571763941726176563326457884416489644189097908134799371 175
UVM_INFO @ 600657155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 35 test runs
otp_ctrl_stress_all_with_rand_reset 78558250954617643216379320651956798368509062318803636633935928823310505282957 148
UVM_INFO @ 979921387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 33829593113029622627773221622866827854988505418316204938265911776814877649586 13445
UVM_INFO @ 12764115932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 11637337511904177882624549825509653684547124343983822195344288710605247300089 98
UVM_INFO @ 236767637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 65250374408534034343071207034102360442087080161031101592801278259607880564173 25196
UVM_INFO @ 1103355418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 37863347554746805551400556837480265903176627419327054298741696121696681382295 92
UVM_INFO @ 85188919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113954204148587698153174349934938180853440174389196072689298009870925306112616 92
UVM_INFO @ 28005969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 68301768298050332285875199777676399648194526866922727147155744061861508603657 92
UVM_INFO @ 28134497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 80910590429762649802607844898963939869382831587814748966151289919355545445147 27673
UVM_INFO @ 7667146628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 1678613631906900630921337907124500649986735212295628073815929288195582558937 15555
UVM_INFO @ 4131045799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62290896443407061494022414766679842592875198310880023492928337223157255164646 1077
UVM_INFO @ 930265066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 39418009395730029981736079919170216304776103597587054766859040406201943484211 92
UVM_INFO @ 426738180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102735990490046894334620610372818289498352916389231305656363598248454089614714 92
UVM_INFO @ 427579227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 64963957765370403568797105475599831818945240984435571238613798333228580551883 5336
UVM_INFO @ 3638239874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18904565877014153696605926588880440422585964746828020520998422956022394228355 4238
UVM_INFO @ 277003743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 55053036985243409748220276797323734500310613652446130925595805528262326837410 92
UVM_INFO @ 106267496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 88834839196996137709633481106505508048750641515747716428340227276047867501020 970
UVM_INFO @ 612831100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 67767508105215079616341983809691346447013064314902835068449995647733187069685 20071
UVM_INFO @ 7592424265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69051099756312892918070783083033644609563009624101651037563992377395935694274 30853
UVM_INFO @ 12728783154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 70710109248873608061252743864373956483611823225715031673314436610371862259205 132
UVM_INFO @ 224009994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9799806614508883215568995422093494758653547132774546838747227663316095929437 92
UVM_INFO @ 28310120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 53787439714231542738001213909407534538448908685111232475177318817347793723470 93
UVM_INFO @ 109494777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 89293235551319428280559994290755671512863895336267956253528200083226951178223 223
UVM_INFO @ 427996595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 7610456438575085618251333721004331350259132922195253309445502741842753158838 293
UVM_INFO @ 138246050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 102571357532016396768871523973875439004770662698772114531130186109205475698688 3301
UVM_INFO @ 7005437189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62277224353130977816978996689986382374553014098301758186814730401915083720152 486
UVM_INFO @ 2962358469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 82840578619949310971169955823805845005989359626741026421737440226017078141600 7153
UVM_INFO @ 879895447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 85464664636552701068473270485415750499443191615251388850460655562257812044381 446
UVM_INFO @ 1769998054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25228938385664649203651610481624491623176831216867380295033971689550789246764 8683
UVM_INFO @ 5545772521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 50889666341284597503948805269455307761676842774335406852810827969184503478255 1325
UVM_INFO @ 16257428106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 104452603673098212305868558689220042039698034221836830341846273621289657796811 5373
UVM_INFO @ 8395971739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 77678620085539689540009801066927039607615204931146345373794811398932733398417 178
UVM_INFO @ 66344454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 103812168838788374355448966184475646477721093860287690256499595968965201258711 666
UVM_INFO @ 249973750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 54689370446691649928757040267786236093553658298822513103371324787210815472719 93
UVM_INFO @ 27672073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 73382397298687570188937681847379578639092237261221115367671237804447779855927 1626
UVM_INFO @ 1163429353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 98044679873975022797683152735234264697673175085401286704792079031834417401556 146
UVM_INFO @ 15503371465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 11 test runs
otp_ctrl_stress_all_with_rand_reset 43372029811504563361273351979888120057441265377314920020270669301696670243585 1014
UVM_INFO @ 773427474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 79817848428169521867690785732366285417701652068900992293281037804408218942057 16497
UVM_INFO @ 788190125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 91766588450849714654448246287007572000579419902412415186046967466872012242318 9950
UVM_INFO @ 4049933645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 69551566580487685530323495005195615635103618375233905991282137852009997414156 2972
UVM_INFO @ 1516425619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 25644041071812539628673198749660801207456785057914650497095091239652618947788 29636
UVM_INFO @ 9063382004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 58483634438728809444997542907083455133085998877494331750964957902572029899376 12247
UVM_INFO @ 6845749821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 42560467374715652187993162326817675614065947014531592907969394726753773933721 5159
UVM_INFO @ 18839055758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81720748253814708797359910478112345543655987150367610356139460491642516771507 22482
UVM_INFO @ 5265411781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 81261533157173474829737441195905275527637571389338738167532492535376733616653 1917
UVM_INFO @ 4793257668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 27842083990035674100091732617795155878085021746167372010747145813380642129083 2063
UVM_INFO @ 13852332265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 113197730490427328584479390804262708666421853430531323928133875587490621426390 5624
UVM_INFO @ 8513836408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 8 test runs
otp_ctrl_csr_mem_rw_with_rand_reset 105132349354100419536629919333441697675998037041984589915432030406896180919389 98
UVM_INFO @ 60178860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_csr_mem_rw_with_rand_reset 106339049706066066832982735039627276557129993363885874944783599030253313618823 92
UVM_INFO @ 29934251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 99484490061512422186460655308225250852530064058287287830419157573182998254628 24128
UVM_INFO @ 52579112996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 9326256427874325958546129260909007810798819064490020109946028740206533019502 16741
UVM_INFO @ 14050989533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18193451428150344551929878430057719776973523245622408054291924789346894399727 7194
UVM_INFO @ 12641461239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 5585017428691500012159927520826220102122001220078299531832241880664533427232 2161
UVM_INFO @ 426429873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 18975523959273073951093825072470165080469204678728678403874343380249483610672 4257
UVM_INFO @ 2523564943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 43275342068966518708261684357111961004318287139880197242294441805342988483597 17482
UVM_INFO @ 14189224473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch 2 test runs
otp_ctrl_stress_all_with_rand_reset 11210882807948141309217816319830761050447908212456033444843465486976993711383 9981
UVM_INFO @ 31998232507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 2681476226407650677876062480753875986598682861658961216638420076288904303368 648
UVM_INFO @ 2836477085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [otp_ctrl_common_vseq] wait timeout occurred! 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 26590542166737021656724773921443468541717364515501393398245876369683493997483 96
UVM_INFO @ 10046760179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 1 test run
otp_ctrl_stress_all_with_rand_reset 39715690366512103094713402459433873014804093681846710580166888306403779330266 1042
UVM_INFO @ 201889574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr a* rdata* readout mismatch 1 test run
otp_ctrl_stress_all_with_rand_reset 114754486900827745287216368066490525750001135377529228385499065753075217309165 92
UVM_INFO @ 746507244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 66092988799080180854226646744109598288701420444719697702908511081063569232379 4386
UVM_INFO @ 925416086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:454) [otp_ctrl_parallel_lc_esc_vseq] wait timeout occurred! 1 test run
otp_ctrl_parallel_lc_esc 94765120033003279311376148589079501144214071570630626129496359499102089951233 89
UVM_INFO @ 10001052667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---