Simulation Results: rom_ctrl/32kb

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.59 %
  • code
  • 99.68 %
  • assert
  • 96.80 %
  • func
  • 99.28 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.81 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.65%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.580s 139.235us 2 2 100.00
csr_hw_reset 5 5 100.00
rom_ctrl_csr_hw_reset 9.270s 351.082us 5 5 100.00
csr_rw 20 20 100.00
rom_ctrl_csr_rw 8.730s 1015.014us 20 20 100.00
csr_bit_bash 5 5 100.00
rom_ctrl_csr_bit_bash 6.610s 283.671us 5 5 100.00
csr_aliasing 5 5 100.00
rom_ctrl_csr_aliasing 5.150s 170.891us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 9.480s 564.360us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rom_ctrl_csr_rw 8.730s 1015.014us 20 20 100.00
rom_ctrl_csr_aliasing 5.150s 170.891us 5 5 100.00
mem_walk 5 5 100.00
rom_ctrl_mem_walk 6.550s 164.476us 5 5 100.00
mem_partial_access 5 5 100.00
rom_ctrl_mem_partial_access 6.260s 555.695us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.900s 181.250us 2 2 100.00
stress_all 20 20 100.00
rom_ctrl_stress_all 32.890s 6647.763us 20 20 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 9.080s 220.451us 2 2 100.00
alert_test 50 50 100.00
rom_ctrl_alert_test 9.490s 546.319us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rom_ctrl_tl_errors 13.360s 8271.184us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rom_ctrl_tl_errors 13.360s 8271.184us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.270s 351.082us 5 5 100.00
rom_ctrl_csr_rw 8.730s 1015.014us 20 20 100.00
rom_ctrl_csr_aliasing 5.150s 170.891us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.850s 131.145us 20 20 100.00
tl_d_partial_access 50 50 100.00
rom_ctrl_csr_hw_reset 9.270s 351.082us 5 5 100.00
rom_ctrl_csr_rw 8.730s 1015.014us 20 20 100.00
rom_ctrl_csr_aliasing 5.150s 170.891us 5 5 100.00
rom_ctrl_same_csr_outstanding 7.850s 131.145us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
passthru_mem_tl_intg_err 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 45.560s 3121.748us 20 20 100.00
tl_intg_err 25 25 100.00
rom_ctrl_sec_cm 276.930s 878.285us 5 5 100.00
rom_ctrl_tl_intg_err 60.450s 337.695us 20 20 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 276.930s 878.285us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 276.930s 878.285us 5 5 100.00
sec_cm_checker_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_checker_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_checker_fsm_local_esc 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_compare_ctrl_flow_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_compare_ctr_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 276.930s 878.285us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 276.930s 878.285us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.580s 139.235us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.580s 139.235us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.580s 139.235us 2 2 100.00
sec_cm_bus_integrity 20 20 100.00
rom_ctrl_tl_intg_err 60.450s 337.695us 20 20 100.00
sec_cm_bus_local_esc 19 22 86.36
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
rom_ctrl_kmac_err_chk 9.080s 220.451us 2 2 100.00
sec_cm_mux_mubi 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_mux_consistency 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_ctrl_redun 17 20 85.00
rom_ctrl_corrupt_sig_fatal_chk 160.680s 11075.371us 17 20 85.00
sec_cm_ctrl_mem_integrity 20 20 100.00
rom_ctrl_passthru_mem_tl_intg_err 45.560s 3121.748us 20 20 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 276.930s 878.285us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 20 20 100.00
rom_ctrl_stress_all_with_rand_reset 435.780s 4154.496us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) 3 test runs
rom_ctrl_corrupt_sig_fatal_chk 78818956032386443863057452946437839747618330713873019949677325809683253134759 84
UVM_INFO @ 339847710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 16485751099683820716332053400312242244883093708423078727530091839422527520098 96
UVM_INFO @ 2050502158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_corrupt_sig_fatal_chk 44922261343839541829750754870177207159270925631418424311082254828707410319370 82
UVM_INFO @ 232719010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---