| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.170s | 222.749us | 2 | 2 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 18.870s | 1703.948us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_rw | 11.680s | 1109.789us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_bit_bash | 9.970s | 212.206us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rom_ctrl_csr_aliasing | 10.400s | 554.917us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_csr_mem_rw_with_rand_reset | 11.640s | 1088.995us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rom_ctrl_csr_rw | 11.680s | 1109.789us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.400s | 554.917us | 5 | 5 | 100.00 | |
| mem_walk | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_walk | 11.360s | 2086.271us | 5 | 5 | 100.00 | |
| mem_partial_access | 5 | 5 | 100.00 | |||
| rom_ctrl_mem_partial_access | 11.600s | 290.497us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| max_throughput_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_max_throughput_chk | 11.900s | 1063.935us | 2 | 2 | 100.00 | |
| stress_all | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all | 61.810s | 4065.676us | 20 | 20 | 100.00 | |
| kmac_err_chk | 2 | 2 | 100.00 | |||
| rom_ctrl_kmac_err_chk | 21.040s | 380.986us | 2 | 2 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rom_ctrl_alert_test | 14.890s | 1084.450us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 15.960s | 1088.693us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_errors | 15.960s | 1088.693us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 18.870s | 1703.948us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 11.680s | 1109.789us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.400s | 554.917us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 14.950s | 1195.841us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rom_ctrl_csr_hw_reset | 18.870s | 1703.948us | 5 | 5 | 100.00 | |
| rom_ctrl_csr_rw | 11.680s | 1109.789us | 20 | 20 | 100.00 | |
| rom_ctrl_csr_aliasing | 10.400s | 554.917us | 5 | 5 | 100.00 | |
| rom_ctrl_same_csr_outstanding | 14.950s | 1195.841us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| corrupt_sig_fatal_chk | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| passthru_mem_tl_intg_err | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 71.310s | 19195.130us | 20 | 20 | 100.00 | |
| tl_intg_err | 25 | 25 | 100.00 | |||
| rom_ctrl_sec_cm | 587.220s | 1826.384us | 5 | 5 | 100.00 | |
| rom_ctrl_tl_intg_err | 136.580s | 3546.461us | 20 | 20 | 100.00 | |
| prim_fsm_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 587.220s | 1826.384us | 5 | 5 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 587.220s | 1826.384us | 5 | 5 | 100.00 | |
| sec_cm_checker_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_checker_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_checker_fsm_local_esc | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctrl_flow_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_compare_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 587.220s | 1826.384us | 5 | 5 | 100.00 | |
| sec_cm_fsm_sparse | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 587.220s | 1826.384us | 5 | 5 | 100.00 | |
| sec_cm_mem_scramble | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.170s | 222.749us | 2 | 2 | 100.00 | |
| sec_cm_mem_digest | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.170s | 222.749us | 2 | 2 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| rom_ctrl_smoke | 9.170s | 222.749us | 2 | 2 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_tl_intg_err | 136.580s | 3546.461us | 20 | 20 | 100.00 | |
| sec_cm_bus_local_esc | 22 | 22 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| rom_ctrl_kmac_err_chk | 21.040s | 380.986us | 2 | 2 | 100.00 | |
| sec_cm_mux_mubi | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_mux_consistency | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_redun | 20 | 20 | 100.00 | |||
| rom_ctrl_corrupt_sig_fatal_chk | 268.840s | 113325.272us | 20 | 20 | 100.00 | |
| sec_cm_ctrl_mem_integrity | 20 | 20 | 100.00 | |||
| rom_ctrl_passthru_mem_tl_intg_err | 71.310s | 19195.130us | 20 | 20 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| rom_ctrl_sec_cm | 587.220s | 1826.384us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 20 | 20 | 100.00 | |||
| rom_ctrl_stress_all_with_rand_reset | 532.080s | 5628.755us | 20 | 20 | 100.00 | |