Simulation Results: rstmgr

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.86 %
  • code
  • 99.68 %
  • assert
  • 98.13 %
  • func
  • 98.76 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 99.38 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
rstmgr_smoke 1.970s 255.245us 50 50 100.00
csr_hw_reset 5 5 100.00
rstmgr_csr_hw_reset 1.350s 158.450us 5 5 100.00
csr_rw 20 20 100.00
rstmgr_csr_rw 1.280s 96.941us 20 20 100.00
csr_bit_bash 5 5 100.00
rstmgr_csr_bit_bash 10.790s 2005.217us 5 5 100.00
csr_aliasing 5 5 100.00
rstmgr_csr_aliasing 2.860s 355.290us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.110s 183.194us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
rstmgr_csr_rw 1.280s 96.941us 20 20 100.00
rstmgr_csr_aliasing 2.860s 355.290us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 50 50 100.00
rstmgr_por_stretcher 1.430s 214.583us 50 50 100.00
sw_rst 50 50 100.00
rstmgr_sw_rst 3.160s 468.628us 50 50 100.00
sw_rst_reset_race 50 50 100.00
rstmgr_sw_rst_reset_race 1.920s 213.529us 50 50 100.00
reset_info 50 50 100.00
rstmgr_reset 8.400s 1739.587us 50 50 100.00
cpu_info 50 50 100.00
rstmgr_reset 8.400s 1739.587us 50 50 100.00
alert_info 50 50 100.00
rstmgr_reset 8.400s 1739.587us 50 50 100.00
reset_info_capture 50 50 100.00
rstmgr_reset 8.400s 1739.587us 50 50 100.00
stress_all 50 50 100.00
rstmgr_stress_all 48.870s 14696.441us 50 50 100.00
alert_test 50 50 100.00
rstmgr_alert_test 1.260s 98.857us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
rstmgr_tl_errors 3.350s 573.947us 20 20 100.00
tl_d_illegal_access 20 20 100.00
rstmgr_tl_errors 3.350s 573.947us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
rstmgr_csr_hw_reset 1.350s 158.450us 5 5 100.00
rstmgr_csr_rw 1.280s 96.941us 20 20 100.00
rstmgr_csr_aliasing 2.860s 355.290us 5 5 100.00
rstmgr_same_csr_outstanding 2.140s 240.076us 20 20 100.00
tl_d_partial_access 50 50 100.00
rstmgr_csr_hw_reset 1.350s 158.450us 5 5 100.00
rstmgr_csr_rw 1.280s 96.941us 20 20 100.00
rstmgr_csr_aliasing 2.860s 355.290us 5 5 100.00
rstmgr_same_csr_outstanding 2.140s 240.076us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
rstmgr_sec_cm 20.400s 16881.374us 5 5 100.00
rstmgr_tl_intg_err 3.790s 817.915us 20 20 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 20.400s 16881.374us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 20.400s 16881.374us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
rstmgr_tl_intg_err 3.790s 817.915us 20 20 100.00
sec_cm_scan_intersig_mubi 50 50 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.640s 188.027us 50 50 100.00
sec_cm_leaf_rst_bkgn_chk 50 50 100.00
rstmgr_leaf_rst_cnsty 8.120s 1965.791us 50 50 100.00
sec_cm_leaf_rst_shadow 50 50 100.00
rstmgr_leaf_rst_shadow_attack 1.780s 302.416us 50 50 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 20.400s 16881.374us 5 5 100.00
sec_cm_sw_rst_config_regwen 20 20 100.00
rstmgr_csr_rw 1.280s 96.941us 20 20 100.00
sec_cm_dump_ctrl_config_regwen 20 20 100.00
rstmgr_csr_rw 1.280s 96.941us 20 20 100.00