| V1 |
|
100.00% |
| V2 |
|
92.92% |
| V2S |
|
100.00% |
| V3 |
|
45.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random | 20 | 20 | 100.00 | |||
| rv_timer_random | 1.940s | 1274.143us | 20 | 20 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 21.459us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| rv_timer_csr_rw | 0.920s | 40.524us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| rv_timer_csr_bit_bash | 3.180s | 953.174us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| rv_timer_csr_aliasing | 1.020s | 114.758us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 | |||
| rv_timer_csr_mem_rw_with_rand_reset | 1.470s | 124.875us | 20 | 20 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| rv_timer_csr_rw | 0.920s | 40.524us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.020s | 114.758us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| random_reset | 3 | 20 | 15.00 | |||
| rv_timer_random_reset | 11.790s | 33862.682us | 3 | 20 | 15.00 | |
| disabled | 20 | 20 | 100.00 | |||
| rv_timer_disabled | 2.820s | 2430.419us | 20 | 20 | 100.00 | |
| cfg_update_on_fly | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 200.650s | 187860.831us | 10 | 10 | 100.00 | |
| no_interrupt_test | 10 | 10 | 100.00 | |||
| rv_timer_cfg_update_on_fly | 200.650s | 187860.831us | 10 | 10 | 100.00 | |
| stress | 20 | 20 | 100.00 | |||
| rv_timer_stress_all | 8.670s | 5640.641us | 20 | 20 | 100.00 | |
| alert_test | 50 | 50 | 100.00 | |||
| rv_timer_alert_test | 0.890s | 12.500us | 50 | 50 | 100.00 | |
| intr_test | 50 | 50 | 100.00 | |||
| rv_timer_intr_test | 0.910s | 15.007us | 50 | 50 | 100.00 | |
| tl_d_oob_addr_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.410s | 742.603us | 20 | 20 | 100.00 | |
| tl_d_illegal_access | 20 | 20 | 100.00 | |||
| rv_timer_tl_errors | 2.410s | 742.603us | 20 | 20 | 100.00 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 21.459us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.920s | 40.524us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.020s | 114.758us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.090s | 110.745us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| rv_timer_csr_hw_reset | 0.900s | 21.459us | 5 | 5 | 100.00 | |
| rv_timer_csr_rw | 0.920s | 40.524us | 20 | 20 | 100.00 | |
| rv_timer_csr_aliasing | 1.020s | 114.758us | 5 | 5 | 100.00 | |
| rv_timer_same_csr_outstanding | 1.090s | 110.745us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 25 | 25 | 100.00 | |||
| rv_timer_sec_cm | 1.190s | 189.089us | 5 | 5 | 100.00 | |
| rv_timer_tl_intg_err | 1.800s | 191.865us | 20 | 20 | 100.00 | |
| sec_cm_bus_integrity | 20 | 20 | 100.00 | |||
| rv_timer_tl_intg_err | 1.800s | 191.865us | 20 | 20 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| min_value | 2 | 10 | 20.00 | |||
| rv_timer_min | 1.440s | 865.612us | 2 | 10 | 20.00 | |
| max_value | 1 | 10 | 10.00 | |||
| rv_timer_max | 1.090s | 42.242us | 1 | 10 | 10.00 | |
| stress_all_with_rand_reset | 15 | 20 | 75.00 | |||
| rv_timer_stress_all_with_rand_reset | 52.530s | 22838.437us | 15 | 20 | 75.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * | 25 test runs | |||
| rv_timer_min | 20239787090168432349934981739895395331717402165134215680262270271641782919413 | 78 |
UVM_INFO @ 327472919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 77088922144749007558069497062491966417671131525814370526855441716000486968448 | 75 |
UVM_INFO @ 96451611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 56927476924126101890740508119165848816077213759245996995875797966015062743324 | 77 |
UVM_INFO @ 70867247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 85851791306133058646130587281495058619201612857887111107546000119494956321495 | 76 |
UVM_INFO @ 865611681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 47816387322919821007294902103503951477410124815257840635131176997929551923068 | 75 |
UVM_INFO @ 47664343289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 87862006789798074711205356504858574426123513428042117631298387636239362193960 | 75 |
UVM_INFO @ 71857895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 18811105897909615616209638805413418151350188627408857856023430194197221024726 | 75 |
UVM_INFO @ 1685979172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 84675700260116580134728275604114091361329593381200528561072367268199902392350 | 76 |
UVM_INFO @ 1184427623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 35072373491282679869066598026855427465357386919854866205896347062903153877237 | 75 |
UVM_INFO @ 4249839502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 48144604633700991076594601031732644787134051553518725025512784424180588260562 | 75 |
UVM_INFO @ 153579784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 61046768720275927760203956039217856263123363407466569010793318251705522714475 | 75 |
UVM_INFO @ 33862682336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 103780509816713448351005708210249140464687255419647796155519513641326440410052 | 75 |
UVM_INFO @ 67574749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 85830646725169868664620843628171033414676002682146157463027651473855793615062 | 76 |
UVM_INFO @ 264511113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 35282023816642090599693364268757397548554332801706388359008697174911366694896 | 76 |
UVM_INFO @ 129935110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 99146231889887919794989952546991426110232048996972359278175779838210561289450 | 77 |
UVM_INFO @ 723123021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_min | 93094916966215267460019121946809165629451508546915623519892357230746572898255 | 75 |
UVM_INFO @ 442360060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 3298104443060938061893838724817946872595386149433406248097107022562315320592 | 76 |
UVM_INFO @ 21793661097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 47556065368698533170119836913126884553339015070417735648809280936976112179068 | 75 |
UVM_INFO @ 83785348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 114317532528876759174781728379591040344726212787300874352664107078881245346993 | 75 |
UVM_INFO @ 1856119530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 50649072711737327693280769521792504701506249738408065437802303531206250181869 | 75 |
UVM_INFO @ 1669218317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 28162844012391406028067655670852120673915382073941515900259368791182556522710 | 75 |
UVM_INFO @ 143926641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 42658873092052995706316006224811528280896542126344682995492360300418779998782 | 75 |
UVM_INFO @ 1358053263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 100412869716009211265084891704710381324709268651419174957732831083484710009266 | 75 |
UVM_INFO @ 15689450999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 71009841831885551912321261633847385654219931528731877079728685805500251451547 | 75 |
UVM_INFO @ 1571901846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_random_reset | 24006847166033188918747503093312053533038134017896779747827667962563187184709 | 75 |
UVM_INFO @ 1011020768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 8 test runs | |||
| rv_timer_max | 84296527355738491493038054882686427194721404538887256702633677713218296624236 | 75 |
UVM_INFO @ 47665080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 100454437533562485440447093814626736341605299604754742358745243187576372841948 | 75 |
UVM_INFO @ 43834672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 81683561148245169292327436852343187609452439769855189211952279557147527239979 | 75 |
UVM_INFO @ 353156646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 111467099917847344764492510433455770793475146835444543063101327803191322517551 | 77 |
UVM_INFO @ 94301548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 13285411525146683203086051603154730602535694832894034912316539634499692058380 | 75 |
UVM_INFO @ 252311868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 2507014327282683181605811246632721276501638112688463339619709267327894098566 | 75 |
UVM_INFO @ 186338047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 50925449580148529433754832146395703742508523236920388675661733432433398846675 | 75 |
UVM_INFO @ 169111542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_max | 64664690195159230031254804496195586632809341254906070924543343471838016258508 | 76 |
UVM_INFO @ 43174368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues | 4 test runs | |||
| rv_timer_stress_all_with_rand_reset | 81882880389412355310859535202382159299637785257757829681731813484925369325248 | 196 |
UVM_INFO @ 4993726525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 60761299359553614298381620770081250273757734652457555857147441062129904081112 | 79 |
UVM_INFO @ 3002571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 2816732317594470884364652648727668879302202051743193886268835831823657785444 | 207 |
UVM_INFO @ 1390890938 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rv_timer_stress_all_with_rand_reset | 34359994865409355123853766808029853085155138992095105110813695602192820868594 | 133 |
UVM_INFO @ 514106551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (rv_timer_scoreboard.sv:346) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) | 1 test run | |||
| rv_timer_max | 82303482580974033819426251929367620128055501576258771218792382706604102993732 | 75 |
UVM_INFO @ 42242035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done) | 1 test run | |||
| rv_timer_stress_all_with_rand_reset | 25488617168311613832341962215698839232866644257590526533744198097427690087200 | 120 |
UVM_INFO @ 1543319800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|