Simulation Results: spi_device/2p

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.07 %
  • code
  • 94.22 %
  • assert
  • 94.74 %
  • func
  • 99.26 %
  • line
  • 98.96 %
  • branch
  • 98.39 %
  • cond
  • 96.63 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_device_flash_and_tpm 436.220s 233419.108us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_device_csr_hw_reset 1.550s 285.382us 5 5 100.00
csr_rw 20 20 100.00
spi_device_csr_rw 3.110s 95.068us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_device_csr_bit_bash 27.290s 1803.505us 5 5 100.00
csr_aliasing 5 5 100.00
spi_device_csr_aliasing 16.060s 602.729us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_device_csr_mem_rw_with_rand_reset 3.990s 163.761us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_device_csr_rw 3.110s 95.068us 20 20 100.00
spi_device_csr_aliasing 16.060s 602.729us 5 5 100.00
mem_walk 5 5 100.00
spi_device_mem_walk 1.060s 21.461us 5 5 100.00
mem_partial_access 5 5 100.00
spi_device_mem_partial_access 2.090s 45.261us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 50 50 100.00
spi_device_csb_read 1.220s 78.130us 50 50 100.00
mem_parity 20 20 100.00
spi_device_mem_parity 1.500s 118.173us 20 20 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 1.170s 18.822us 1 1 100.00
tpm_read 50 50 100.00
spi_device_tpm_rw 8.320s 208.247us 50 50 100.00
tpm_write 50 50 100.00
spi_device_tpm_rw 8.320s 208.247us 50 50 100.00
tpm_hw_reg 100 100 100.00
spi_device_tpm_read_hw_reg 17.340s 8824.369us 50 50 100.00
spi_device_tpm_sts_read 1.560s 1611.591us 50 50 100.00
tpm_fully_random_case 50 50 100.00
spi_device_tpm_all 46.670s 10983.153us 50 50 100.00
pass_cmd_filtering 100 100 100.00
spi_device_pass_cmd_filtering 24.830s 5392.043us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
pass_addr_translation 100 100 100.00
spi_device_pass_addr_payload_swap 25.930s 10068.936us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
pass_payload_translation 100 100 100.00
spi_device_pass_addr_payload_swap 25.930s 10068.936us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
cmd_info_slots 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
cmd_read_status 100 100 100.00
spi_device_intercept 30.290s 24492.522us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
cmd_read_jedec 100 100 100.00
spi_device_intercept 30.290s 24492.522us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
cmd_read_sfdp 100 100 100.00
spi_device_intercept 30.290s 24492.522us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
cmd_fast_read 100 100 100.00
spi_device_intercept 30.290s 24492.522us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
cmd_read_pipeline 100 100 100.00
spi_device_intercept 30.290s 24492.522us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
flash_cmd_upload 50 50 100.00
spi_device_upload 29.850s 11378.855us 50 50 100.00
mailbox_command 50 50 100.00
spi_device_mailbox 102.090s 36608.541us 50 50 100.00
mailbox_cross_outside_command 50 50 100.00
spi_device_mailbox 102.090s 36608.541us 50 50 100.00
mailbox_cross_inside_command 50 50 100.00
spi_device_mailbox 102.090s 36608.541us 50 50 100.00
cmd_read_buffer 100 100 100.00
spi_device_flash_mode 59.720s 18386.287us 50 50 100.00
spi_device_read_buffer_direct 14.420s 1303.338us 50 50 100.00
cmd_dummy_cycle 100 100 100.00
spi_device_mailbox 102.090s 36608.541us 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
quad_spi 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
dual_spi 50 50 100.00
spi_device_flash_all 310.460s 257804.194us 50 50 100.00
4b_3b_feature 50 50 100.00
spi_device_cfg_cmd 15.190s 4914.874us 50 50 100.00
write_enable_disable 50 50 100.00
spi_device_cfg_cmd 15.190s 4914.874us 50 50 100.00
TPM_with_flash_or_passthrough_mode 50 50 100.00
spi_device_flash_and_tpm 436.220s 233419.108us 50 50 100.00
tpm_and_flash_trans_with_min_inactive_time 50 50 100.00
spi_device_flash_and_tpm_min_idle 363.580s 215767.522us 50 50 100.00
stress_all 50 50 100.00
spi_device_stress_all 1023.580s 259867.069us 50 50 100.00
alert_test 50 50 100.00
spi_device_alert_test 1.140s 27.160us 50 50 100.00
intr_test 50 50 100.00
spi_device_intr_test 1.230s 24.514us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_device_tl_errors 5.290s 396.407us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_device_tl_errors 5.290s 396.407us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_device_csr_hw_reset 1.550s 285.382us 5 5 100.00
spi_device_csr_rw 3.110s 95.068us 20 20 100.00
spi_device_csr_aliasing 16.060s 602.729us 5 5 100.00
spi_device_same_csr_outstanding 4.930s 386.048us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_device_csr_hw_reset 1.550s 285.382us 5 5 100.00
spi_device_csr_rw 3.110s 95.068us 20 20 100.00
spi_device_csr_aliasing 16.060s 602.729us 5 5 100.00
spi_device_same_csr_outstanding 4.930s 386.048us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_device_sec_cm 1.750s 95.608us 5 5 100.00
spi_device_tl_intg_err 25.830s 1006.081us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
spi_device_tl_intg_err 25.830s 1006.081us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 50 50 100.00
spi_device_flash_mode_ignore_cmds 383.730s 776641.442us 50 50 100.00