Simulation Results: spi_host

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.81 %
  • code
  • 95.03 %
  • assert
  • 95.64 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.74%
V2S
100.00%
unmapped
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
spi_host_smoke 119.000s 9881.446us 50 50 100.00
csr_hw_reset 5 5 100.00
spi_host_csr_hw_reset 2.000s 35.010us 5 5 100.00
csr_rw 20 20 100.00
spi_host_csr_rw 2.000s 18.445us 20 20 100.00
csr_bit_bash 5 5 100.00
spi_host_csr_bit_bash 4.000s 941.896us 5 5 100.00
csr_aliasing 5 5 100.00
spi_host_csr_aliasing 2.000s 32.509us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 41.332us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
spi_host_csr_rw 2.000s 18.445us 20 20 100.00
spi_host_csr_aliasing 2.000s 32.509us 5 5 100.00
mem_walk 5 5 100.00
spi_host_mem_walk 2.000s 17.539us 5 5 100.00
mem_partial_access 5 5 100.00
spi_host_mem_partial_access 2.000s 56.457us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 50 50 100.00
spi_host_performance 2.000s 30.468us 50 50 100.00
error_event_intr 150 150 100.00
spi_host_overflow_underflow 32.000s 2050.928us 50 50 100.00
spi_host_error_cmd 2.000s 24.255us 50 50 100.00
spi_host_event 622.000s 19896.732us 50 50 100.00
clock_rate 50 50 100.00
spi_host_speed 8.000s 412.058us 50 50 100.00
speed 50 50 100.00
spi_host_speed 8.000s 412.058us 50 50 100.00
chip_select_timing 50 50 100.00
spi_host_speed 8.000s 412.058us 50 50 100.00
sw_reset 50 50 100.00
spi_host_sw_reset 89.000s 2864.296us 50 50 100.00
passthrough_mode 50 50 100.00
spi_host_passthrough_mode 2.000s 165.257us 50 50 100.00
cpol_cpha 50 50 100.00
spi_host_speed 8.000s 412.058us 50 50 100.00
full_cycle 50 50 100.00
spi_host_speed 8.000s 412.058us 50 50 100.00
duplex 50 50 100.00
spi_host_smoke 119.000s 9881.446us 50 50 100.00
tx_rx_only 50 50 100.00
spi_host_smoke 119.000s 9881.446us 50 50 100.00
stress_all 49 50 98.00
spi_host_stress_all 1730.000s 1000000.000us 49 50 98.00
spien 50 50 100.00
spi_host_spien 229.000s 13825.144us 50 50 100.00
stall 49 50 98.00
spi_host_status_stall 1132.000s 586758.127us 49 50 98.00
Idlecsbactive 50 50 100.00
spi_host_idlecsbactive 34.000s 1736.973us 50 50 100.00
data_fifo_status 50 50 100.00
spi_host_overflow_underflow 32.000s 2050.928us 50 50 100.00
alert_test 50 50 100.00
spi_host_alert_test 2.000s 40.064us 50 50 100.00
intr_test 50 50 100.00
spi_host_intr_test 2.000s 22.279us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
spi_host_tl_errors 3.000s 142.048us 20 20 100.00
tl_d_illegal_access 20 20 100.00
spi_host_tl_errors 3.000s 142.048us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 35.010us 5 5 100.00
spi_host_csr_rw 2.000s 18.445us 20 20 100.00
spi_host_csr_aliasing 2.000s 32.509us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 16.916us 20 20 100.00
tl_d_partial_access 50 50 100.00
spi_host_csr_hw_reset 2.000s 35.010us 5 5 100.00
spi_host_csr_rw 2.000s 18.445us 20 20 100.00
spi_host_csr_aliasing 2.000s 32.509us 5 5 100.00
spi_host_same_csr_outstanding 2.000s 16.916us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
spi_host_tl_intg_err 3.000s 181.806us 20 20 100.00
spi_host_sec_cm 2.000s 66.363us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
spi_host_tl_intg_err 3.000s 181.806us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 9 10 90.00
spi_host_upper_range_clkdiv 640.000s 30543.397us 9 10 90.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 3 test runs
spi_host_upper_range_clkdiv 56860139542649191946255876592442871900647267147519903308923530460251528309094 149
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_stress_all 62969999055307410224564422395129884138817352027326540266542388094379263794733 129
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
spi_host_status_stall 66767842929600712834752424049869040889166213760530852340634115013382033122141 2749
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---