Simulation Results: sram_ctrl/main

 
16/05/2026 23:17:21 DVSim: v1.34.0 sha: 5eeb50d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.52 %
  • code
  • 96.88 %
  • assert
  • 96.46 %
  • func
  • 96.22 %
  • block
  • 96.22 %
  • line
  • 96.96 %
  • branch
  • 94.49 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
sram_ctrl_smoke 10.000s 2858.024us 5 5 100.00
csr_hw_reset 5 5 100.00
sram_ctrl_csr_hw_reset 2.000s 63.164us 5 5 100.00
csr_rw 20 20 100.00
sram_ctrl_csr_rw 2.000s 42.073us 20 20 100.00
csr_bit_bash 5 5 100.00
sram_ctrl_csr_bit_bash 3.000s 170.862us 5 5 100.00
csr_aliasing 5 5 100.00
sram_ctrl_csr_aliasing 2.000s 12.369us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 6.000s 1697.544us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
sram_ctrl_csr_rw 2.000s 42.073us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 12.369us 5 5 100.00
mem_walk 5 5 100.00
sram_ctrl_mem_walk 286.000s 159014.614us 5 5 100.00
mem_partial_access 5 5 100.00
sram_ctrl_mem_partial_access 127.000s 8054.082us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 5 5 100.00
sram_ctrl_multiple_keys 51.000s 39893.026us 5 5 100.00
stress_pipeline 5 5 100.00
sram_ctrl_stress_pipeline 219.000s 21980.429us 5 5 100.00
bijection 5 5 100.00
sram_ctrl_bijection 174.000s 9530.543us 5 5 100.00
access_during_key_req 5 5 100.00
sram_ctrl_access_during_key_req 68.000s 15667.402us 5 5 100.00
lc_escalation 5 5 100.00
sram_ctrl_lc_escalation 80.000s 16122.505us 5 5 100.00
executable 5 5 100.00
sram_ctrl_executable 53.000s 6403.841us 5 5 100.00
partial_access 10 10 100.00
sram_ctrl_partial_access 6.000s 1432.966us 5 5 100.00
sram_ctrl_partial_access_b2b 350.000s 350630.619us 5 5 100.00
max_throughput 15 15 100.00
sram_ctrl_max_throughput 9.000s 5106.339us 5 5 100.00
sram_ctrl_throughput_w_partial_write 9.000s 5547.909us 5 5 100.00
sram_ctrl_throughput_w_readback 8.000s 9551.571us 5 5 100.00
regwen 5 5 100.00
sram_ctrl_regwen 13.000s 1763.089us 5 5 100.00
ram_cfg 5 5 100.00
sram_ctrl_ram_cfg 5.000s 1350.501us 5 5 100.00
stress_all 5 5 100.00
sram_ctrl_stress_all 615.000s 774685.106us 5 5 100.00
alert_test 50 50 100.00
sram_ctrl_alert_test 2.000s 49.694us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 207.081us 20 20 100.00
tl_d_illegal_access 20 20 100.00
sram_ctrl_tl_errors 6.000s 207.081us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 63.164us 5 5 100.00
sram_ctrl_csr_rw 2.000s 42.073us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 12.369us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 53.373us 20 20 100.00
tl_d_partial_access 50 50 100.00
sram_ctrl_csr_hw_reset 2.000s 63.164us 5 5 100.00
sram_ctrl_csr_rw 2.000s 42.073us 20 20 100.00
sram_ctrl_csr_aliasing 2.000s 12.369us 5 5 100.00
sram_ctrl_same_csr_outstanding 2.000s 53.373us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 38.000s 29508.734us 20 20 100.00
tl_intg_err 25 25 100.00
sram_ctrl_sec_cm 5.000s 589.817us 5 5 100.00
sram_ctrl_tl_intg_err 4.000s 203.339us 20 20 100.00
prim_count_check 5 5 100.00
sram_ctrl_sec_cm 5.000s 589.817us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
sram_ctrl_tl_intg_err 4.000s 203.339us 20 20 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
sram_ctrl_regwen 13.000s 1763.089us 5 5 100.00
sec_cm_readback_config_regwen 5 5 100.00
sram_ctrl_regwen 13.000s 1763.089us 5 5 100.00
sec_cm_exec_config_regwen 20 20 100.00
sram_ctrl_csr_rw 2.000s 42.073us 20 20 100.00
sec_cm_exec_config_mubi 5 5 100.00
sram_ctrl_executable 53.000s 6403.841us 5 5 100.00
sec_cm_exec_intersig_mubi 5 5 100.00
sram_ctrl_executable 53.000s 6403.841us 5 5 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 5 5 100.00
sram_ctrl_executable 53.000s 6403.841us 5 5 100.00
sec_cm_lc_escalate_en_intersig_mubi 5 5 100.00
sram_ctrl_lc_escalation 80.000s 16122.505us 5 5 100.00
sec_cm_prim_ram_ctrl_mubi 5 5 100.00
sram_ctrl_mubi_enc_err 8.000s 2791.439us 5 5 100.00
sec_cm_mem_integrity 20 20 100.00
sram_ctrl_passthru_mem_tl_intg_err 38.000s 29508.734us 20 20 100.00
sec_cm_mem_readback 5 5 100.00
sram_ctrl_readback_err 8.000s 2767.202us 5 5 100.00
sec_cm_mem_scramble 5 5 100.00
sram_ctrl_smoke 10.000s 2858.024us 5 5 100.00
sec_cm_addr_scramble 5 5 100.00
sram_ctrl_smoke 10.000s 2858.024us 5 5 100.00
sec_cm_instr_bus_lc_gated 5 5 100.00
sram_ctrl_executable 53.000s 6403.841us 5 5 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 5 5 100.00
sram_ctrl_sec_cm 5.000s 589.817us 5 5 100.00
sec_cm_key_global_esc 5 5 100.00
sram_ctrl_lc_escalation 80.000s 16122.505us 5 5 100.00
sec_cm_key_local_esc 5 5 100.00
sram_ctrl_sec_cm 5.000s 589.817us 5 5 100.00
sec_cm_init_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 589.817us 5 5 100.00
sec_cm_scramble_key_sideload 5 5 100.00
sram_ctrl_smoke 10.000s 2858.024us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
sram_ctrl_sec_cm 5.000s 589.817us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 5 100.00
sram_ctrl_stress_all_with_rand_reset 51.000s 3694.943us 5 5 100.00