Simulation Results: aes/masked

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.44 %
  • code
  • 96.68 %
  • assert
  • 98.53 %
  • func
  • 97.10 %
  • block
  • 97.08 %
  • line
  • 98.21 %
  • branch
  • 92.75 %
  • toggle
  • 97.99 %
  • FSM
  • 97.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
93.36%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 15.000s 272.255us 1 1 100.00
smoke 50 50 100.00
aes_smoke 27.000s 144.940us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 33.000s 97.273us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 34.000s 71.897us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 40.000s 2425.463us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 34.000s 334.174us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 34.000s 154.437us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 34.000s 71.897us 20 20 100.00
aes_csr_aliasing 34.000s 334.174us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 27.000s 144.940us 50 50 100.00
aes_config_error 35.000s 66.318us 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
key_length 150 150 100.00
aes_smoke 27.000s 144.940us 50 50 100.00
aes_config_error 35.000s 66.318us 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
back2back 100 100 100.00
aes_stress 33.000s 863.868us 50 50 100.00
aes_b2b 86.000s 1334.605us 50 50 100.00
backpressure 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 27.000s 144.940us 50 50 100.00
aes_config_error 35.000s 66.318us 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
aes_alert_reset 37.000s 780.898us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 34.000s 68.640us 50 50 100.00
aes_config_error 35.000s 66.318us 50 50 100.00
aes_alert_reset 37.000s 780.898us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 36.000s 295.914us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 40.000s 726.850us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 37.000s 780.898us 50 50 100.00
stress 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
sideload 100 100 100.00
aes_stress 33.000s 863.868us 50 50 100.00
aes_sideload 48.000s 2205.077us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 36.000s 89.484us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 40.000s 689.707us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 34.000s 55.776us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 22.000s 347.149us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 22.000s 347.149us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 33.000s 97.273us 5 5 100.00
aes_csr_rw 34.000s 71.897us 20 20 100.00
aes_csr_aliasing 34.000s 334.174us 5 5 100.00
aes_same_csr_outstanding 31.000s 145.858us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 33.000s 97.273us 5 5 100.00
aes_csr_rw 34.000s 71.897us 20 20 100.00
aes_csr_aliasing 34.000s 334.174us 5 5 100.00
aes_same_csr_outstanding 31.000s 145.858us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 48 50 96.00
aes_reseed 135.000s 12359.393us 48 50 96.00
fault_inject 630 700 90.00
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
shadow_reg_update_error 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 31.000s 327.395us 19 20 95.00
tl_intg_err 25 25 100.00
aes_sec_cm 32.000s 555.430us 5 5 100.00
aes_tl_intg_err 19.000s 114.301us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 19.000s 114.301us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 37.000s 780.898us 50 50 100.00
sec_cm_main_config_shadow 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
sec_cm_gcm_config_shadow 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
sec_cm_main_config_sparse 212 220 96.36
aes_smoke 27.000s 144.940us 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
aes_alert_reset 37.000s 780.898us 50 50 100.00
aes_core_fi 160.000s 10028.623us 62 70 88.57
sec_cm_gcm_config_sparse 162 170 95.29
aes_config_error 35.000s 66.318us 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
aes_core_fi 160.000s 10028.623us 62 70 88.57
sec_cm_aux_config_shadow 20 20 100.00
aes_shadow_reg_errors 30.000s 79.177us 20 20 100.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 33.000s 80.316us 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 33.000s 863.868us 50 50 100.00
aes_sideload 48.000s 2205.077us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 33.000s 80.316us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 33.000s 80.316us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 33.000s 80.316us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 33.000s 80.316us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 33.000s 80.316us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 33.000s 863.868us 50 50 100.00
sec_cm_main_fsm_sparse 47 50 94.00
aes_fi 45.000s 705.683us 47 50 94.00
sec_cm_main_fsm_redun 679 750 90.53
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_sparse 47 50 94.00
aes_fi 45.000s 705.683us 47 50 94.00
sec_cm_cipher_fsm_redun 630 700 90.00
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
sec_cm_cipher_ctr_redun 321 350 91.71
aes_cipher_fi 61.000s 0.000us 321 350 91.71
sec_cm_ctr_fsm_sparse 47 50 94.00
aes_fi 45.000s 705.683us 47 50 94.00
sec_cm_ctr_fsm_redun 358 400 89.50
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_sparse 47 50 94.00
aes_fi 45.000s 705.683us 47 50 94.00
sec_cm_ctrl_sparse 679 750 90.53
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 37.000s 780.898us 50 50 100.00
sec_cm_main_fsm_local_esc 679 750 90.53
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_cipher_fsm_local_esc 679 750 90.53
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_ctr_fsm_local_esc 358 400 89.50
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_ctr_fi 61.000s 0.000us 49 50 98.00
sec_cm_ghash_fsm_local_esc 47 50 94.00
aes_fi 45.000s 705.683us 47 50 94.00
sec_cm_data_reg_local_esc 630 700 90.00
aes_fi 45.000s 705.683us 47 50 94.00
aes_control_fi 61.000s 0.000us 262 300 87.33
aes_cipher_fi 61.000s 0.000us 321 350 91.71
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
aes_stress_all_with_rand_reset 50.000s 7994.741us 2 10 20.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 23 test runs
aes_control_fi 29295486014872272515678328808690907503518485180807302845427361246767069280102 151
UVM_INFO @ 10018788530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 49133054001184686592715013241844472501697654426157736538278056130238997873203 153
UVM_INFO @ 10014510715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 3428604166135765030137677589217179628900783837814031068743501525738875091636 146
UVM_INFO @ 10011513142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 100118354320985161162747011501972315281633839358015369310400927085569611195450 148
UVM_INFO @ 10005273112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 86118797042325987734675666402508913460398945605143921688335523283649564500513 144
UVM_INFO @ 10006713371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 38412926214199501528806855274775259455072510679548901477301652345782016056127 149
UVM_INFO @ 10005617220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 45710244331544203082542715519931467379089554777894964115903380086117432662728 140
UVM_INFO @ 10012705096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 59355185948689018287861846026281124456984560255222486037105807785234010863764 154
UVM_INFO @ 10010577288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 57103173841690699871033841628371935403844968355239128808138670218306543087368 148
UVM_INFO @ 10008134254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 21979730228177597698762172983681918095784541884934033732118754423880484217413 149
UVM_INFO @ 10016120378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 94024741640296931869151144746661974592341819205873976043309311943336022648212 144
UVM_INFO @ 10022093873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 8018060340214544533475187492492658709848696029538420859961977011507336186614 140
UVM_INFO @ 10007015129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 71999201262735199916946216752746372207481847260245370435946038091258037450560 151
UVM_INFO @ 10015311823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 21475743153317646546408514682706150842302282525154624967159469256684184821537 151
UVM_INFO @ 10003550191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 80773883367984720535118652256498150501993694978290295959167264114786735742000 145
UVM_INFO @ 10009214165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 90526154136101213072334248043508513673853166490958048797327165886145170131988 148
UVM_INFO @ 10032337612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 60446457973834179909752717836765569452722626850506215858933775713029225187196 152
UVM_INFO @ 10031885264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 79519209705939445761467064043497544401136484264577521998085870706265544030538 141
UVM_INFO @ 10021257791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 77167956503482394063137498778790420555417830523825136781075154731665708134620 139
UVM_INFO @ 10023349493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 48469044856109539600563553597797287728003966823148542176871448279707923750214 138
UVM_INFO @ 10012677751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 72516653702126335198851633066128163652693669228974247147434736199604388779640 140
UVM_INFO @ 10054068726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 38559691727060872292962452797610604426536004100057738977563611616625362870220 152
UVM_INFO @ 10012506957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 108920912763414161602981897228242866125846044946991987407325419994001033622701 147
UVM_INFO @ 10005151034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 23 test runs
aes_ctr_fi 61147897389195962205706211555791307108755574567905826374871494903391459257718 None
aes_control_fi 58473731044011311455293083457096433998980255321614807264635131722646825449857 None
aes_control_fi 61221745143801991073021508984026229998812069139006118241559634739079241015595 None
aes_cipher_fi 100914883704458351447919222969442415453684881964412086165986972023951118869914 None
aes_control_fi 94969188144396291807891403996404697791823836684283608953655716121980075480917 None
aes_control_fi 64480640701645590162204071207354575712664325829264604119453175305080521771689 None
aes_control_fi 57909519332921071347477696674918677254721595480106717619459798498217198975132 None
aes_control_fi 71731639996889374175543084992739801729152296736689702048482564536463810693651 None
aes_cipher_fi 115419452848263065153965823324058574733564288061030247906120462165145039215939 None
aes_cipher_fi 32124097791071692536045614601087559033034868958492153401068812566014211020557 None
aes_control_fi 107637981659252784123258659278026569625972581938675480913643999411253053504709 None
aes_control_fi 109598525246644216471849072522082312610126721430032857572681619096836393184929 None
aes_control_fi 105130293878123489119874181712155631869611129656738570272606778503082745794769 None
aes_control_fi 5320862251689836353876916641410501801932710739424835935790115053392294163970 None
aes_control_fi 12176689233672041897901418259581294792665026390584739052488447359724445069692 None
aes_cipher_fi 112169045838365573447722405234348918669946912413256783739250267493129754397714 None
aes_control_fi 43227851463616165762854569455818184435514901251406036712373451323736927162806 None
aes_control_fi 26235659423373816998371344145625754668687604460131868018736830954010085530782 None
aes_cipher_fi 91459615101687119554078244808880277167982357120357022248919947884598693835365 None
aes_control_fi 93095169213738789889373502443810695297076491063489625925891529783186714302859 None
aes_cipher_fi 104998342116610123983767733666949353861733760359412229609468982707191830575966 None
aes_cipher_fi 1439362317264408054762901462134654038414682179362338672092461339701757668761 None
aes_control_fi 88277894972906581767077830164212458463388018409813371073700988466533330155776 None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 22 test runs
aes_cipher_fi 105421474738306741441772990258829889245484384381752619243915713151938403330108 139
UVM_INFO @ 10022479192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 96583185921531514893915837299851162785107747362014499208984986944314099233519 140
UVM_INFO @ 10045804376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 100134326382092685375129261764599136341193098180628610985388320591174625807653 151
UVM_INFO @ 10028792494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 1079246996683639821473772910934264487545867221995283143105431840665618654153 146
UVM_INFO @ 10012630076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 38047979793403076969236498378995289467417361276231659308527092377878120515813 138
UVM_INFO @ 10009839191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 998821076878357354602031274829403798434668521655722345187039544310487255082 142
UVM_INFO @ 10067987320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 42048884145076222250788455300695623180871810778595656047518518974522075283854 147
UVM_INFO @ 10009481243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 85004349817885091369133932155753323468567162379244014885292682503321654133733 153
UVM_INFO @ 10010409554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 12290975392261598375764121580972366473194772532119065035207494577117946487523 138
UVM_INFO @ 10002668077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 104490846663801748335670594562790270208921616956744833890347183749280902456136 153
UVM_INFO @ 10007687500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 30178246801614263374769289559911614433955088168723848428493778633990171349468 143
UVM_INFO @ 10020533639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 47313012451913385897771087278920400395163178688958200249202090550132092197739 150
UVM_INFO @ 10006429425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 25349727183321445191415654669863035418547410931717154742610322507514914443233 144
UVM_INFO @ 10007263348 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 36332225827663390483647306257550428036276100101687322027097540183959840211929 139
UVM_INFO @ 10021870372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 91542508987615668338719496577884564898920235082297352836870680904845158499761 138
UVM_INFO @ 10083198798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 4984233078768983923562911896103820868808810226998856909188933851965353928101 151
UVM_INFO @ 10043672641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 49740312254386293406697783455891579644476580612644701363618744693629267266413 140
UVM_INFO @ 10014525490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97323802410559659573296233525520832133208175085497536216011715410950999560122 142
UVM_INFO @ 10013344932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 86432999806857093073757382452325243689523294671555092131869867460975101114240 148
UVM_INFO @ 10009139587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 57359653945922522730600646406076385428674518999243380724110564799531183743190 144
UVM_INFO @ 10008293590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 12946897821426156119578125833136526934499935957497573719998926609060373799365 139
UVM_INFO @ 10008521736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 39602944261656670666218361522627432713555107908931674081082413394114599219220 149
UVM_INFO @ 10023453573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 6 test runs
aes_core_fi 38113361204571608946017893622771152856484086776421125420481194347744834403046 149
UVM_INFO @ 10052439245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 49807461724844558761468019167901123394951122903985049944336066813802125376579 146
UVM_INFO @ 10027532070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 56708609785490450276992653579799654141720994936034641559013247394705797349046 142
UVM_INFO @ 10045014645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 113523149740588676105817332110567606018803696936675712559047328075205421960712 149
UVM_INFO @ 10034082535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 12862462645073832993928486437038436569779202869132631544736619319162784497324 145
UVM_INFO @ 10012024956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 68817731989986982540586881037127744973656167361035163615705203116175651368919 150
UVM_INFO @ 10016872672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 2 test runs
aes_stress_all_with_rand_reset 83730872229699045897520863436835927435975864331968496970418583182786700046905 638
UVM_INFO @ 2415892172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 53389366361076454711810082761724999822646612683778562868569228365543668581103 310
UVM_INFO @ 4822367394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all_with_rand_reset 65163176716541171358234610682681379597703108596148610089664824787704665104855 1780
UVM_INFO @ 7994740504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 112796506900389310351876092476033770723566535220795659337808848151822809214607 1412
UVM_INFO @ 7050889999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 2 test runs
aes_stress_all_with_rand_reset 73982844786759656625366414659146112155026448526598081686119988391108369537634 1021
UVM_INFO @ 1392174403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 36297132945210261115978019366961535484701646204668243089113070459376816182817 142
UVM_INFO @ 19331855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error 2 test runs
aes_fi 79164989880665779597079819712481908873979973026871583973173580044109897908974 869
UVM_INFO @ 20101003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_fi 42004658798693120406848149439845732374827252454358321321098067983217074953870 533
UVM_INFO @ 226254361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 42484714774578925434116097725269585179556778904308097840411924498072904330068 714
UVM_INFO @ 686780083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 1 test run
aes_stress_all_with_rand_reset 76479112978077679447169385293745955624979664797919057490130139953691181216430 219
UVM_INFO @ 72935878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) 1 test run
aes_core_fi 32590002106263133305412802291012241596952982310215880116538850894203601182913 143
UVM_INFO @ 10028622959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors_with_csr_rw 451189321349875496393536590929861878810903539236293750280430172562621757038 107
UVM_INFO @ 58910332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_fi_vseq.sv:95) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset 1 test run
aes_fi 64776457974357893318902056923328786531384848934016800994849309891446212640132 6346
UVM_INFO @ 181691523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_reseed 110903429885986134574820987014406068490543404304702306894164942828585840882242 14362
TEST FAILED MESSAGES DID NOT MATCH
0 68 c9 ab 0
1 00 57 a9 0
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) 1 test run
aes_reseed 48391952087930226236398065705962363466043681111967843132540458282320172331787 313
UVM_INFO @ 4046521665 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 95903971139309012105853777829245660315804572609827791969275341153166148080389 144
UVM_INFO @ 10048712414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---