Simulation Results: aes/unmasked

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 93.18 %
  • assert
  • 98.11 %
  • func
  • 96.52 %
  • block
  • 94.28 %
  • line
  • 96.00 %
  • branch
  • 87.62 %
  • toggle
  • 97.99 %
  • FSM
  • 91.11 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.96%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 3.000s 114.053us 1 1 100.00
smoke 50 50 100.00
aes_smoke 3.000s 251.422us 50 50 100.00
csr_hw_reset 5 5 100.00
aes_csr_hw_reset 3.000s 236.769us 5 5 100.00
csr_rw 20 20 100.00
aes_csr_rw 3.000s 136.673us 20 20 100.00
csr_bit_bash 5 5 100.00
aes_csr_bit_bash 6.000s 710.137us 5 5 100.00
csr_aliasing 5 5 100.00
aes_csr_aliasing 3.000s 125.657us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 145.879us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
aes_csr_rw 3.000s 136.673us 20 20 100.00
aes_csr_aliasing 3.000s 125.657us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 150 150 100.00
aes_smoke 3.000s 251.422us 50 50 100.00
aes_config_error 4.000s 698.387us 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
key_length 150 150 100.00
aes_smoke 3.000s 251.422us 50 50 100.00
aes_config_error 4.000s 698.387us 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
back2back 100 100 100.00
aes_stress 4.000s 252.160us 50 50 100.00
aes_b2b 8.000s 357.446us 50 50 100.00
backpressure 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
multi_message 200 200 100.00
aes_smoke 3.000s 251.422us 50 50 100.00
aes_config_error 4.000s 698.387us 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
aes_alert_reset 4.000s 295.193us 50 50 100.00
failure_test 150 150 100.00
aes_man_cfg_err 3.000s 115.392us 50 50 100.00
aes_config_error 4.000s 698.387us 50 50 100.00
aes_alert_reset 4.000s 295.193us 50 50 100.00
trigger_clear_test 50 50 100.00
aes_clear 4.000s 1301.410us 50 50 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 209.277us 1 1 100.00
reset_recovery 50 50 100.00
aes_alert_reset 4.000s 295.193us 50 50 100.00
stress 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
sideload 100 100 100.00
aes_stress 4.000s 252.160us 50 50 100.00
aes_sideload 8.000s 463.013us 50 50 100.00
deinitialization 50 50 100.00
aes_deinit 4.000s 478.540us 50 50 100.00
stress_all 10 10 100.00
aes_stress_all 23.000s 1358.406us 10 10 100.00
alert_test 50 50 100.00
aes_alert_test 3.000s 83.506us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
aes_tl_errors 4.000s 1151.633us 20 20 100.00
tl_d_illegal_access 20 20 100.00
aes_tl_errors 4.000s 1151.633us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
aes_csr_hw_reset 3.000s 236.769us 5 5 100.00
aes_csr_rw 3.000s 136.673us 20 20 100.00
aes_csr_aliasing 3.000s 125.657us 5 5 100.00
aes_same_csr_outstanding 4.000s 859.133us 20 20 100.00
tl_d_partial_access 50 50 100.00
aes_csr_hw_reset 3.000s 236.769us 5 5 100.00
aes_csr_rw 3.000s 136.673us 20 20 100.00
aes_csr_aliasing 3.000s 125.657us 5 5 100.00
aes_same_csr_outstanding 4.000s 859.133us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 50 50 100.00
aes_reseed 5.000s 330.665us 50 50 100.00
fault_inject 621 700 88.71
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
shadow_reg_update_error 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
shadow_reg_read_clear_staged_value 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
shadow_reg_storage_error 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
shadowed_reset_glitch 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
aes_shadow_reg_errors_with_csr_rw 4.000s 668.835us 19 20 95.00
tl_intg_err 25 25 100.00
aes_sec_cm 4.000s 5389.049us 5 5 100.00
aes_tl_intg_err 4.000s 429.280us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
aes_tl_intg_err 4.000s 429.280us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
aes_alert_reset 4.000s 295.193us 50 50 100.00
sec_cm_main_config_shadow 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
sec_cm_gcm_config_shadow 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
sec_cm_main_config_sparse 214 220 97.27
aes_smoke 3.000s 251.422us 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
aes_alert_reset 4.000s 295.193us 50 50 100.00
aes_core_fi 68.000s 10035.456us 64 70 91.43
sec_cm_gcm_config_sparse 164 170 96.47
aes_config_error 4.000s 698.387us 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
aes_core_fi 68.000s 10035.456us 64 70 91.43
sec_cm_aux_config_shadow 19 20 95.00
aes_shadow_reg_errors 3.000s 158.249us 19 20 95.00
sec_cm_aux_config_regwen 100 100 100.00
aes_readability 3.000s 69.220us 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
sec_cm_key_sideload 100 100 100.00
aes_stress 4.000s 252.160us 50 50 100.00
aes_sideload 8.000s 463.013us 50 50 100.00
sec_cm_key_sw_unreadable 50 50 100.00
aes_readability 3.000s 69.220us 50 50 100.00
sec_cm_data_reg_sw_unreadable 50 50 100.00
aes_readability 3.000s 69.220us 50 50 100.00
sec_cm_key_sec_wipe 50 50 100.00
aes_readability 3.000s 69.220us 50 50 100.00
sec_cm_iv_config_sec_wipe 50 50 100.00
aes_readability 3.000s 69.220us 50 50 100.00
sec_cm_data_reg_sec_wipe 50 50 100.00
aes_readability 3.000s 69.220us 50 50 100.00
sec_cm_data_reg_key_sca 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
sec_cm_key_masking 50 50 100.00
aes_stress 4.000s 252.160us 50 50 100.00
sec_cm_main_fsm_sparse 50 50 100.00
aes_fi 4.000s 90.266us 50 50 100.00
sec_cm_main_fsm_redun 671 750 89.47
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
aes_ctr_fi 4.000s 364.366us 50 50 100.00
sec_cm_cipher_fsm_sparse 50 50 100.00
aes_fi 4.000s 90.266us 50 50 100.00
sec_cm_cipher_fsm_redun 621 700 88.71
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
sec_cm_cipher_ctr_redun 308 350 88.00
aes_cipher_fi 61.000s 0.000us 308 350 88.00
sec_cm_ctr_fsm_sparse 50 50 100.00
aes_fi 4.000s 90.266us 50 50 100.00
sec_cm_ctr_fsm_redun 363 400 90.75
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_ctr_fi 4.000s 364.366us 50 50 100.00
sec_cm_ghash_fsm_sparse 50 50 100.00
aes_fi 4.000s 90.266us 50 50 100.00
sec_cm_ctrl_sparse 671 750 89.47
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
aes_ctr_fi 4.000s 364.366us 50 50 100.00
sec_cm_main_fsm_global_esc 50 50 100.00
aes_alert_reset 4.000s 295.193us 50 50 100.00
sec_cm_main_fsm_local_esc 671 750 89.47
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
aes_ctr_fi 4.000s 364.366us 50 50 100.00
sec_cm_cipher_fsm_local_esc 671 750 89.47
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
aes_ctr_fi 4.000s 364.366us 50 50 100.00
sec_cm_ctr_fsm_local_esc 363 400 90.75
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_ctr_fi 4.000s 364.366us 50 50 100.00
sec_cm_ghash_fsm_local_esc 50 50 100.00
aes_fi 4.000s 90.266us 50 50 100.00
sec_cm_data_reg_local_esc 621 700 88.71
aes_fi 4.000s 90.266us 50 50 100.00
aes_control_fi 62.135s 0.000us 263 300 87.67
aes_cipher_fi 61.000s 0.000us 308 350 88.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
aes_stress_all_with_rand_reset 91.000s 7459.289us 2 10 20.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! 30 test runs
aes_cipher_fi 39211902242837407503035975752483985322336462171978920575623548196741118454929 147
UVM_INFO @ 10020315203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 112091063160366789146893048561111875703059620837954276984615403951135927715059 139
UVM_INFO @ 10021953452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 49568048339622962631797098276837018883517778023538598652942698859900889272914 145
UVM_INFO @ 10006339157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 101742655824624781052381034947589185679677608026397058398230304647040833407265 154
UVM_INFO @ 10005877104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 69939159496524097981356632018246625474329374824797687624578133199192999026696 147
UVM_INFO @ 10003206190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 85495258490439781904315756576253299980933125570255780350815604738066788530325 152
UVM_INFO @ 10006360165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 105351288460870672566163323022314544710100922231207622182527592337736335334224 145
UVM_INFO @ 10003458553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 94234196616656385679180395328789892756843801005356805896571506335068420260210 150
UVM_INFO @ 10007948932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 101550816145730725574933902047846197614664139014870170437677532586951931821116 146
UVM_INFO @ 10008012944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 83714008769652859424021078646398869469018805967175744818585408430382554182960 147
UVM_INFO @ 10013957122 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 35918910629647611869745699715700064052485420221661971073354872508553816043308 138
UVM_INFO @ 10004671948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 115609233562014462623625313035699654023938790119791099513350219720356260607526 146
UVM_INFO @ 10005860638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 79788688495387211925613183477538536419057910027224396115439302877126145161196 143
UVM_INFO @ 10009263131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 107782007499284903837696105768251492757959731316877538293655951912931965119218 141
UVM_INFO @ 10058600017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 50845829714525546123709238933262694914179300867819913590897345458907012780504 147
UVM_INFO @ 10008066650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 48145775735243435350141334070568173328998436146122521386236442625408263886004 147
UVM_INFO @ 10042729730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 7680161606603229378092964571097550374461133476197557085039730813098833205274 148
UVM_INFO @ 10006168980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 106511436531448297201159885144246469140779516904844083142717254464820223975668 144
UVM_INFO @ 10013998139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 110510535022204128985698800045973318245912440920088156262408909598775458344868 140
UVM_INFO @ 10015971470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 60857447003894031566657278914033781319185131491406330050906471195404197843382 142
UVM_INFO @ 10007745543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 81339914563653021234872611576096913005315851345636200886552101327297258431410 147
UVM_INFO @ 10008038065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 60784197253983670827123139085392098395934002286580874151161766895189715262456 139
UVM_INFO @ 10024629598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 89716563063744853602458043756594261204098983600883272726540644966503655045600 152
UVM_INFO @ 10010226767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 36082894531906762389574336434115674976585248865839211143032103054389156035292 149
UVM_INFO @ 10011475604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97597865578268312388179497636957119273552842663797933461263468246175494738893 140
UVM_INFO @ 10008811822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 60884751587864711566304009662535369162954986236714244626488345578361530706367 148
UVM_INFO @ 10005195224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 16069711834110060532491600988002511123872610616375131189511153436734251228948 154
UVM_INFO @ 10006767624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 101140223906105104309574780176016264844951459911783439373617027812478843300204 140
UVM_INFO @ 10002511565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 97770054364310661450526474025636374271394005775697967769659323982325392141669 149
UVM_INFO @ 10006980753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_cipher_fi 28545649577503062686420325095931505321620497114805945482670436682754777061478 151
UVM_INFO @ 10033449044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 25 test runs
aes_control_fi 99568717684034706156736686125341670696082096854011053914614456294374798073969 145
UVM_INFO @ 10009614108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 12301277098404909278644401325871468760796408808386711677651701155379425660983 146
UVM_INFO @ 10009950755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 92061374134750699172223373452050175865726402449269946682980348286229879806831 148
UVM_INFO @ 10004401601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 69304629025583765265925566910054012943069564569872632767768541997100873078065 154
UVM_INFO @ 10005092199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 92250509154382269621344277285623988731965721899288169311946435322309100460981 150
UVM_INFO @ 10013453646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 83461821936003632635355184167531238086731881460440283437212929919878724154703 142
UVM_INFO @ 10006456379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 53153458942781350797860692425485786258540677887512859444259371725595400815500 141
UVM_INFO @ 10033311979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 105765796197760425489250876038788359836072370618943819346034571881530411389765 144
UVM_INFO @ 10004256213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 94762650267752252751071631265058630864632314628899895381685600380294710410627 145
UVM_INFO @ 10015101524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 108022566404457367694533129190251537560878478059583894161217178608622986900098 146
UVM_INFO @ 10020344472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 20635595983556318688392985527833285584831963783115459591018030679630984100672 139
UVM_INFO @ 10013781540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 40515235502546616730340496324195725255824168908082062990428170995275981989520 143
UVM_INFO @ 10013038972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 92569985053382389508445305650999132193409741966352196334167009221117323851559 149
UVM_INFO @ 10043797611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 34062410440350755258914638655678025795642891728695784208971864749782972313580 145
UVM_INFO @ 10011973523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39115517409823878109780704778182399628474906835392459525666833696807959265357 146
UVM_INFO @ 10017544867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 97664270411680254189810516851655039628736603064632563670048791547220902534431 145
UVM_INFO @ 10010315454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 35200147356975064130994169614327428683140071318798984301889774055606950924781 151
UVM_INFO @ 10007763371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 40774678429990319787199694995389752525378653933117496257584956086552259484709 149
UVM_INFO @ 10015139768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 4566524633732640732733945928965464518922384731084065133919641396884130759542 150
UVM_INFO @ 10003159618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93017729743520257325799241567733876694738194562035737352108774030387168285419 143
UVM_INFO @ 10006582254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 39845998637884613001870606724737474514648804091284019490021362169041951314034 149
UVM_INFO @ 10064704037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93611869160391174524740422839505369622502783255237373667581631915749534274104 145
UVM_INFO @ 10012502366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 269358189674039361842628304446661104775658201000873945645474355074942981156 140
UVM_INFO @ 10011714400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 108152661570535378617116619064861181690726802718745688363226428860446193592 148
UVM_INFO @ 10022293479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_control_fi 93754161854591302302262841916323657464595942159240176695689960365656534117675 146
UVM_INFO @ 10004920209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 24 test runs
aes_control_fi 19265988638209550177108759406777623255674229516547399983137696380537672826939 None
aes_cipher_fi 56124360191831046088656873853088763720772166745803365954973161583525510637368 None
aes_cipher_fi 32086879390090070347269144536979872021921684934437398229695563618065232816679 None
aes_control_fi 103333309277960955370018948383839054515485361602773622016236219505288660870069 None
aes_cipher_fi 103644139146349235391019812166270766538190423280220987916656134762811381373927 None
aes_cipher_fi 77265302489846995233258385146083444051407633880179415105421020537463384832713 None
aes_control_fi 16525476861893034040762987042134370858396488360781666160707143245912680684774 None
aes_cipher_fi 45546064597690467651809282509592785914301770979164532952410436892778560435804 None
aes_control_fi 64973037506569067248381000919309882752638977980456519698032153636199173918162 None
aes_cipher_fi 8295179373168857511653758714365176638228126646216016255228611226620790316778 None
aes_cipher_fi 98468724539164044477345836761216428335262156376056180202088733253316545423297 None
aes_cipher_fi 68344289835322037545823958057275771227096803213969688095434377199681860632571 None
aes_control_fi 64613119399065163167192863690930833745467291934363871868946502065517488955520 None
aes_control_fi 3362888063435305576248525871411415068060142166440899024096274109132483987315 None
aes_cipher_fi 112041444955473574518393797499219201908843936227481248259370576552266340307688 None
aes_control_fi 16801466108089467037523141490021579345838943620026035237678072071304214557838 None
aes_control_fi 95512216113369694303785329236126230071664222049025572691725660122992974364389 None
aes_control_fi 81321714248586491578009632473178112788126617175968844223154646372266414743047 None
aes_control_fi 106161668424258171665523110415057176564520630386033257632134655236217256875593 None
aes_control_fi 67349640510770992024918874317776591578596060646357125355539069447089479192922 None
aes_control_fi 96542767486748312979749579429523907302954580372615390506349278615382751617716 None
aes_cipher_fi 22145378179451139973338619411181933785853674222665188316302498742543365022071 None
aes_cipher_fi 54316849351671720142861132386783076313265528203243272581209255753589651320876 None
aes_cipher_fi 67505997277490476822924081729073227821402369958537769815141399867336472617916 None
UVM_FATAL (aes_base_vseq.sv:76) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 21861474915798986399844872457119974206777821266479473108942296330653074607095 167
UVM_INFO @ 48916516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 58161399083914925562710663100107620727315001938680767019870173296596180945577 823
UVM_INFO @ 4008491152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 43050880903968424925588254961209497852274119602052199516429290558361255222001 892
UVM_INFO @ 3168373657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:76) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) 3 test runs
aes_stress_all_with_rand_reset 27538269081389239831922164080419938204772445219506429829139841915810441942195 166
UVM_INFO @ 60120877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 105893346182168679618939487389334258394415701917905561997596655091882111109925 2034
UVM_INFO @ 700625780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 36632758385484066473292148204207546839098807933436633456680063210280628676335 248
UVM_INFO @ 468595545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred! 3 test runs
aes_core_fi 6115751149533993595014698154335733038693279720699042428734219500603935353908 140
UVM_INFO @ 10018491718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 20104280578869592541234928349488990067038364115289532817102040756026057538656 145
UVM_INFO @ 10002687606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 52415465866491016594542888934286071737540861609240039084254388059074057880039 146
UVM_INFO @ 10004822270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all_with_rand_reset 21223570590198893621815850037623542566975823406839575120984208682736686505747 591
UVM_INFO @ 474079634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 3030427835604159304668757450897618367065116998890276024058751364640872309173 473
UVM_INFO @ 243790008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:93) [aes_core_fi_vseq] wait timeout occurred! 2 test runs
aes_core_fi 7609716081062218914592633410192006761103633453596786511788315446474323356197 143
UVM_INFO @ 10010192760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_core_fi 71371249871199406622630970616723421982663956653626557556297371760599148490763 140
UVM_INFO @ 10012038056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block_extended.ctrl_shadowed reset value: * 1 test run
aes_shadow_reg_errors 102974634826273147937664258889295150301171275125817722061898366446545172358757 106
UVM_INFO @ 3888338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1381) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
aes_shadow_reg_errors_with_csr_rw 16630424006897298464652131254749822946419872934386963372515477395869095113615 106
UVM_INFO @ 37747301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:618) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout aes_reg_block_extended.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) 1 test run
aes_core_fi 75183620143380435711973639040191249269730239232687852634093137255790007772576 141
UVM_INFO @ 10035456017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---