| V1 |
|
94.55% |
| V2 |
|
91.03% |
| V2S |
|
83.33% |
| V3 |
|
86.16% |
| unmapped |
|
58.06% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_example_tests | 12 | 12 | 100.00 | |||
| chip_sw_example_flash | 207.300s | 2506.632us | 3 | 3 | 100.00 | |
| chip_sw_example_rom | 108.810s | 2800.455us | 3 | 3 | 100.00 | |
| chip_sw_example_manufacturer | 197.740s | 2685.355us | 3 | 3 | 100.00 | |
| chip_sw_example_concurrency | 206.610s | 2950.118us | 3 | 3 | 100.00 | |
| csr_hw_reset | 5 | 5 | 100.00 | |||
| chip_csr_hw_reset | 369.280s | 6385.691us | 5 | 5 | 100.00 | |
| csr_rw | 20 | 20 | 100.00 | |||
| chip_csr_rw | 639.510s | 6112.326us | 20 | 20 | 100.00 | |
| csr_bit_bash | 5 | 5 | 100.00 | |||
| chip_csr_bit_bash | 1028.570s | 12210.415us | 5 | 5 | 100.00 | |
| csr_aliasing | 5 | 5 | 100.00 | |||
| chip_csr_aliasing | 5500.920s | 36814.233us | 5 | 5 | 100.00 | |
| csr_mem_rw_with_rand_reset | 8 | 20 | 40.00 | |||
| chip_csr_mem_rw_with_rand_reset | 895.400s | 12124.245us | 8 | 20 | 40.00 | |
| regwen_csr_and_corresponding_lockable_csr | 25 | 25 | 100.00 | |||
| chip_csr_aliasing | 5500.920s | 36814.233us | 5 | 5 | 100.00 | |
| chip_csr_rw | 639.510s | 6112.326us | 20 | 20 | 100.00 | |
| xbar_smoke | 100 | 100 | 100.00 | |||
| xbar_smoke | 12.300s | 247.585us | 100 | 100 | 100.00 | |
| chip_sw_gpio_out | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 419.030s | 4627.597us | 3 | 3 | 100.00 | |
| chip_sw_gpio_in | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 419.030s | 4627.597us | 3 | 3 | 100.00 | |
| chip_sw_gpio_irq | 3 | 3 | 100.00 | |||
| chip_sw_gpio | 419.030s | 4627.597us | 3 | 3 | 100.00 | |
| chip_sw_uart_tx_rx | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 577.720s | 4269.874us | 5 | 5 | 100.00 | |
| chip_sw_uart_rx_overflow | 20 | 20 | 100.00 | |||
| chip_sw_uart_tx_rx | 577.720s | 4269.874us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx1 | 519.460s | 4048.252us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx2 | 492.140s | 4088.791us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_idx3 | 526.260s | 4814.152us | 5 | 5 | 100.00 | |
| chip_sw_uart_baud_rate | 20 | 20 | 100.00 | |||
| chip_sw_uart_rand_baudrate | 2510.850s | 13397.912us | 20 | 20 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq | 10 | 10 | 100.00 | |||
| chip_sw_uart_tx_rx_alt_clk_freq | 2202.780s | 12589.331us | 5 | 5 | 100.00 | |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 1419.900s | 13196.836us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_pin_mux | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 314.980s | 5132.788us | 10 | 10 | 100.00 | |
| chip_padctrl_attributes | 10 | 10 | 100.00 | |||
| chip_padctrl_attributes | 314.980s | 5132.788us | 10 | 10 | 100.00 | |
| chip_sw_sleep_pin_mio_dio_val | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_mio_dio_val | 264.650s | 3177.156us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pin_wake | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_wake | 367.320s | 5933.545us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pin_retention | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pin_retention | 255.850s | 3682.576us | 3 | 3 | 100.00 | |
| chip_sw_tap_strap_sampling | 20 | 20 | 100.00 | |||
| chip_tap_straps_dev | 1268.240s | 14119.312us | 5 | 5 | 100.00 | |
| chip_tap_straps_testunlock0 | 482.560s | 7776.945us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 666.890s | 7762.701us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1500.650s | 16014.849us | 5 | 5 | 100.00 | |
| chip_sw_pattgen_ios | 3 | 3 | 100.00 | |||
| chip_sw_pattgen_ios | 219.320s | 2974.373us | 3 | 3 | 100.00 | |
| chip_sw_sleep_pwm_pulses | 3 | 3 | 100.00 | |||
| chip_sw_sleep_pwm_pulses | 1058.030s | 9559.684us | 3 | 3 | 100.00 | |
| chip_sw_data_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 703.030s | 6868.836us | 6 | 6 | 100.00 | |
| chip_sw_instruction_integrity | 6 | 6 | 100.00 | |||
| chip_sw_data_integrity_escalation | 703.030s | 6868.836us | 6 | 6 | 100.00 | |
| chip_sw_ast_clk_outputs | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 790.040s | 7811.574us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_rst_inputs | 0 | 3 | 0.00 | |||
| chip_sw_ast_clk_rst_inputs | 2114.380s | 15797.372us | 0 | 3 | 0.00 | |
| chip_sw_ast_sys_clk_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 473.440s | 4674.472us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 785.080s | 5842.003us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5021.640s | 18897.032us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 254.500s | 2917.979us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1085.900s | 8454.728us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 288.300s | 3391.692us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 1588.470s | 12125.046us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 259.370s | 3718.401us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 582.500s | 5906.566us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 215.550s | 3400.139us | 3 | 3 | 100.00 | |
| chip_sw_ast_usb_clk_calib | 1 | 1 | 100.00 | |||
| chip_sw_usb_ast_clk_calib | 264.700s | 3325.924us | 1 | 1 | 100.00 | |
| chip_sw_sensor_ctrl_ast_alerts | 6 | 8 | 75.00 | |||
| chip_sw_sensor_ctrl_alert | 903.030s | 8953.354us | 3 | 5 | 60.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 359.360s | 5292.934us | 3 | 3 | 100.00 | |
| chip_sw_sensor_ctrl_ast_status | 3 | 3 | 100.00 | |||
| chip_sw_sensor_ctrl_status | 226.050s | 3445.444us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 359.360s | 5292.934us | 3 | 3 | 100.00 | |
| chip_sw_smoketest | 51 | 51 | 100.00 | |||
| chip_sw_flash_scrambling_smoketest | 175.930s | 3456.246us | 3 | 3 | 100.00 | |
| chip_sw_aes_smoketest | 271.260s | 3032.921us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_smoketest | 240.510s | 3662.009us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_smoketest | 237.690s | 2759.001us | 3 | 3 | 100.00 | |
| chip_sw_csrng_smoketest | 240.710s | 2687.846us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_smoketest | 1334.480s | 7828.606us | 3 | 3 | 100.00 | |
| chip_sw_gpio_smoketest | 295.960s | 3737.844us | 3 | 3 | 100.00 | |
| chip_sw_hmac_smoketest | 333.740s | 3339.364us | 3 | 3 | 100.00 | |
| chip_sw_kmac_smoketest | 264.740s | 2959.535us | 3 | 3 | 100.00 | |
| chip_sw_otbn_smoketest | 1320.170s | 7474.567us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 440.390s | 6477.837us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usbdev_smoketest | 401.240s | 7034.526us | 3 | 3 | 100.00 | |
| chip_sw_rv_plic_smoketest | 238.460s | 3323.828us | 3 | 3 | 100.00 | |
| chip_sw_rv_timer_smoketest | 252.330s | 3407.614us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_smoketest | 231.600s | 3279.153us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_smoketest | 220.660s | 2437.395us | 3 | 3 | 100.00 | |
| chip_sw_uart_smoketest | 220.050s | 3421.290us | 3 | 3 | 100.00 | |
| chip_sw_otp_smoketest | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_smoketest | 217.400s | 3472.836us | 3 | 3 | 100.00 | |
| chip_sw_rom_functests | 0 | 3 | 0.00 | |||
| rom_keymgr_functest | 560.220s | 5911.396us | 0 | 3 | 0.00 | |
| chip_sw_boot | 3 | 3 | 100.00 | |||
| chip_sw_uart_tx_rx_bootstrap | 12494.650s | 63642.738us | 3 | 3 | 100.00 | |
| chip_sw_secure_boot | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 4018.110s | 16725.689us | 3 | 3 | 100.00 | |
| chip_sw_rom_raw_unlock | 0 | 3 | 0.00 | |||
| rom_raw_unlock | 206.544s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_power_idle_load | 0 | 3 | 0.00 | |||
| chip_sw_power_idle_load | 242.860s | 3287.479us | 0 | 3 | 0.00 | |
| chip_sw_power_sleep_load | 0 | 3 | 0.00 | |||
| chip_sw_power_sleep_load | 272.730s | 3760.324us | 0 | 3 | 0.00 | |
| chip_sw_exit_test_unlocked_bootstrap | 3 | 3 | 100.00 | |||
| chip_sw_exit_test_unlocked_bootstrap | 11213.710s | 55097.454us | 3 | 3 | 100.00 | |
| chip_sw_inject_scramble_seed | 3 | 3 | 100.00 | |||
| chip_sw_inject_scramble_seed | 12116.010s | 58434.859us | 3 | 3 | 100.00 | |
| tl_d_oob_addr_access | 5 | 30 | 16.67 | |||
| chip_tl_errors | 213.360s | 3776.648us | 5 | 30 | 16.67 | |
| tl_d_illegal_access | 5 | 30 | 16.67 | |||
| chip_tl_errors | 213.360s | 3776.648us | 5 | 30 | 16.67 | |
| tl_d_outstanding_access | 50 | 50 | 100.00 | |||
| chip_csr_aliasing | 5500.920s | 36814.233us | 5 | 5 | 100.00 | |
| chip_same_csr_outstanding | 4196.800s | 30860.907us | 20 | 20 | 100.00 | |
| chip_csr_hw_reset | 369.280s | 6385.691us | 5 | 5 | 100.00 | |
| chip_csr_rw | 639.510s | 6112.326us | 20 | 20 | 100.00 | |
| tl_d_partial_access | 50 | 50 | 100.00 | |||
| chip_csr_aliasing | 5500.920s | 36814.233us | 5 | 5 | 100.00 | |
| chip_same_csr_outstanding | 4196.800s | 30860.907us | 20 | 20 | 100.00 | |
| chip_csr_hw_reset | 369.280s | 6385.691us | 5 | 5 | 100.00 | |
| chip_csr_rw | 639.510s | 6112.326us | 20 | 20 | 100.00 | |
| xbar_base_random_sequence | 100 | 100 | 100.00 | |||
| xbar_random | 79.220s | 2666.601us | 100 | 100 | 100.00 | |
| xbar_random_delay | 600 | 600 | 100.00 | |||
| xbar_smoke_zero_delays | 7.980s | 58.615us | 100 | 100 | 100.00 | |
| xbar_smoke_large_delays | 106.040s | 10095.792us | 100 | 100 | 100.00 | |
| xbar_smoke_slow_rsp | 101.470s | 6162.379us | 100 | 100 | 100.00 | |
| xbar_random_zero_delays | 52.810s | 621.690us | 100 | 100 | 100.00 | |
| xbar_random_large_delays | 448.770s | 53509.538us | 100 | 100 | 100.00 | |
| xbar_random_slow_rsp | 424.530s | 33019.944us | 100 | 100 | 100.00 | |
| xbar_unmapped_address | 200 | 200 | 100.00 | |||
| xbar_unmapped_addr | 68.940s | 1331.608us | 100 | 100 | 100.00 | |
| xbar_error_and_unmapped_addr | 55.490s | 1318.617us | 100 | 100 | 100.00 | |
| xbar_error_cases | 200 | 200 | 100.00 | |||
| xbar_error_random | 87.420s | 2472.106us | 100 | 100 | 100.00 | |
| xbar_error_and_unmapped_addr | 55.490s | 1318.617us | 100 | 100 | 100.00 | |
| xbar_all_access_same_device | 200 | 200 | 100.00 | |||
| xbar_access_same_device | 138.890s | 3000.885us | 100 | 100 | 100.00 | |
| xbar_access_same_device_slow_rsp | 941.430s | 84909.196us | 100 | 100 | 100.00 | |
| xbar_all_hosts_use_same_source_id | 100 | 100 | 100.00 | |||
| xbar_same_source | 71.230s | 2620.251us | 100 | 100 | 100.00 | |
| xbar_stress_all | 200 | 200 | 100.00 | |||
| xbar_stress_all | 639.280s | 19483.764us | 100 | 100 | 100.00 | |
| xbar_stress_all_with_error | 515.980s | 21124.456us | 100 | 100 | 100.00 | |
| xbar_stress_with_reset | 200 | 200 | 100.00 | |||
| xbar_stress_all_with_rand_reset | 767.690s | 8860.823us | 100 | 100 | 100.00 | |
| xbar_stress_all_with_reset_error | 760.590s | 25648.385us | 100 | 100 | 100.00 | |
| rom_e2e_smoke | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 4018.110s | 16725.689us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_output | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_output | 3428.770s | 27906.977us | 3 | 3 | 100.00 | |
| rom_e2e_shutdown_exception_c | 3 | 3 | 100.00 | |||
| rom_e2e_shutdown_exception_c | 3863.670s | 15767.719us | 3 | 3 | 100.00 | |
| rom_e2e_boot_policy_valid | 0 | 15 | 0.00 | |||
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 154.742s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 11.439s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 11.873s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 10.435s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 11.673s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 162.336s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 10.848s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 11.758s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 11.429s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 11.477s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 170.790s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 12.291s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 12.357s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 11.843s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 11.239s | 0.000us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always | 0 | 15 | 0.00 | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 34.010s | 10.280us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 25.020s | 10.220us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 27.620s | 10.400us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 26.430s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 23.990s | 10.220us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 19.910s | 10.360us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 30.250s | 10.300us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 24.530s | 10.240us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 23.210s | 10.120us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 26.730s | 10.280us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 35.780s | 10.200us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 26.790s | 10.340us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 30.950s | 10.100us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 32.740s | 10.340us | 0 | 1 | 0.00 | |
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 22.510s | 10.320us | 0 | 1 | 0.00 | |
| rom_e2e_asm_init | 0 | 15 | 0.00 | |||
| rom_e2e_asm_init_test_unlocked0 | 102.845s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_dev | 12.037s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod | 12.198s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_prod_end | 11.870s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_asm_init_rma | 12.018s | 0.000us | 0 | 3 | 0.00 | |
| rom_e2e_keymgr_init | 8 | 9 | 88.89 | |||
| rom_e2e_keymgr_init_rom_ext_meas | 7967.040s | 30049.875us | 3 | 3 | 100.00 | |
| rom_e2e_keymgr_init_rom_ext_no_meas | 7557.260s | 29945.118us | 3 | 3 | 100.00 | |
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 7827.200s | 28194.975us | 2 | 3 | 66.67 | |
| rom_e2e_static_critical | 3 | 3 | 100.00 | |||
| rom_e2e_static_critical | 4256.690s | 17143.422us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_debug_cable_irq | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.173s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 0 | 3 | 0.00 | |||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.173s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_aes_enc | 6 | 6 | 100.00 | |||
| chip_sw_aes_enc | 227.140s | 2826.645us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 254.500s | 2917.979us | 3 | 3 | 100.00 | |
| chip_sw_aes_entropy | 3 | 3 | 100.00 | |||
| chip_sw_aes_entropy | 218.760s | 3072.378us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 3 | 3 | 100.00 | |||
| chip_sw_aes_idle | 233.690s | 3259.609us | 3 | 3 | 100.00 | |
| chip_sw_aes_sideload | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 1991.320s | 11661.139us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_alerts | 0 | 3 | 0.00 | |||
| chip_sw_alert_test | 255.430s | 3697.310us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_escalations | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 467.780s | 6236.794us | 3 | 3 | 100.00 | |
| chip_sw_all_escalation_resets | 94 | 100 | 94.00 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| chip_sw_alert_handler_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 753.510s | 5656.631us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 367.660s | 3940.886us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 524.970s | 4766.265us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_entropy | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_entropy | 265.290s | 3500.631us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_crashdump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1728.510s | 12926.232us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_timeout | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_timeout | 464.200s | 5471.844us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 0 | 90 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 302.600s | 3619.587us | 0 | 90 | 0.00 | |
| chip_sw_alert_handler_lpg_sleep_mode_pings | 0 | 3 | 0.00 | |||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 14400.202s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_alert_handler_lpg_clock_off | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1680.950s | 8800.208us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_lpg_reset_toggle | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1486.710s | 8427.353us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_ping_ok | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_ping_ok | 1089.130s | 7981.120us | 3 | 3 | 100.00 | |
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_reverse_ping_in_deep_sleep | 13343.630s | 255868.343us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wakeup_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 364.210s | 4405.083us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_smoketest | 440.390s | 6477.837us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bark_irq | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_irq | 364.210s | 4405.083us | 3 | 3 | 100.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 2 | 3 | 66.67 | |||
| chip_sw_aon_timer_wdog_bite_reset | 824.580s | 9044.719us | 2 | 3 | 66.67 | |
| chip_sw_aon_timer_sleep_wdog_bite_reset | 2 | 3 | 66.67 | |||
| chip_sw_aon_timer_wdog_bite_reset | 824.580s | 9044.719us | 2 | 3 | 66.67 | |
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 5 | 5 | 100.00 | |||
| chip_sw_aon_timer_sleep_wdog_sleep_pause | 494.960s | 7284.682us | 5 | 5 | 100.00 | |
| chip_sw_aon_timer_wdog_lc_escalate | 3 | 3 | 100.00 | |||
| chip_sw_aon_timer_wdog_lc_escalate | 540.390s | 6115.361us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_idle_trans | 12 | 12 | 100.00 | |||
| chip_sw_otbn_randomness | 801.540s | 6458.835us | 3 | 3 | 100.00 | |
| chip_sw_aes_idle | 233.690s | 3259.609us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_idle | 275.520s | 3035.017us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 190.530s | 2678.456us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_trans | 12 | 12 | 100.00 | |||
| chip_sw_clkmgr_off_aes_trans | 381.890s | 4603.263us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_hmac_trans | 440.990s | 5396.100us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_kmac_trans | 444.290s | 4393.176us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_otbn_trans | 446.580s | 4535.933us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_off_peri | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_off_peri | 1129.260s | 10138.973us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_div | 21 | 21 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 569.220s | 4614.830us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 557.690s | 4846.464us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 549.890s | 4037.680us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 543.390s | 4585.736us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 555.080s | 4479.056us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 540.290s | 5101.160us | 3 | 3 | 100.00 | |
| chip_sw_ast_clk_outputs | 790.040s | 7811.574us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_lc | 951.050s | 15078.906us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw | 6 | 6 | 100.00 | |||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 549.890s | 4037.680us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 543.390s | 4585.736us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 30 | 30 | 100.00 | |||
| chip_sw_flash_ctrl_ops_jitter_en | 473.440s | 4674.472us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 785.080s | 5842.003us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5021.640s | 18897.032us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en | 254.500s | 2917.979us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs_jitter | 1085.900s | 8454.728us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 288.300s | 3391.692us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 1588.470s | 12125.046us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 259.370s | 3718.401us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 582.500s | 5906.566us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_jitter | 215.550s | 3400.139us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_extended_range | 33 | 33 | 100.00 | |||
| chip_sw_clkmgr_jitter_reduced_freq | 194.460s | 2506.812us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 474.980s | 4603.381us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 876.240s | 7806.083us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 5124.200s | 24952.322us | 3 | 3 | 100.00 | |
| chip_sw_aes_enc_jitter_en_reduced_freq | 243.770s | 3524.187us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en_reduced_freq | 235.470s | 3432.816us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 1604.850s | 13327.180us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 273.030s | 4201.635us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 556.850s | 5230.538us | 3 | 3 | 100.00 | |
| chip_sw_flash_init_reduced_freq | 1720.090s | 22492.149us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_concurrency_reduced_freq | 22155.760s | 134042.348us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_deep_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_ast_clk_outputs | 790.040s | 7811.574us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_sleep_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_sleep_frequency | 508.100s | 5166.829us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_reset_frequency | 3 | 3 | 100.00 | |||
| chip_sw_clkmgr_reset_frequency | 340.700s | 3792.966us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_escalation_reset | 94 | 100 | 94.00 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| chip_sw_clkmgr_alert_handler_clock_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_clkoff | 1680.950s | 8800.208us | 3 | 3 | 100.00 | |
| chip_sw_csrng_edn_cmd | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3356.580s | 24464.419us | 3 | 3 | 100.00 | |
| chip_sw_csrng_fuse_en_sw_app_read | 0 | 3 | 0.00 | |||
| chip_sw_csrng_fuse_en_sw_app_read_test | 201.750s | 2890.840us | 0 | 3 | 0.00 | |
| chip_sw_csrng_lc_hw_debug_en | 3 | 3 | 100.00 | |||
| chip_sw_csrng_lc_hw_debug_en_test | 668.400s | 8552.102us | 3 | 3 | 100.00 | |
| chip_sw_csrng_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_csrng_kat_test | 299.140s | 3041.777us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 16 | 16 | 100.00 | |||
| chip_sw_csrng_edn_concurrency | 8696.780s | 36491.754us | 10 | 10 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 256.650s | 3377.752us | 3 | 3 | 100.00 | |
| chip_sw_edn_entropy_reqs | 1066.960s | 6862.218us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_ast_rng_req | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_ast_rng_req | 256.650s | 3377.752us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_csrng | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_csrng | 3356.580s | 24464.419us | 3 | 3 | 100.00 | |
| chip_sw_entropy_src_known_answer_tests | 3 | 3 | 100.00 | |||
| chip_sw_entropy_src_kat_test | 214.740s | 3238.575us | 3 | 3 | 100.00 | |
| chip_sw_flash_init | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1858.530s | 24193.144us | 3 | 3 | 100.00 | |
| chip_sw_flash_host_access | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_access | 784.870s | 6232.311us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_access_jitter_en | 785.080s | 5842.003us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops | 6 | 6 | 100.00 | |||
| chip_sw_flash_ctrl_ops | 509.830s | 4073.619us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_ops_jitter_en | 473.440s | 4674.472us | 3 | 3 | 100.00 | |
| chip_sw_flash_rma_unlocked | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 5068.680s | 44565.426us | 3 | 3 | 100.00 | |
| chip_sw_flash_scramble | 3 | 3 | 100.00 | |||
| chip_sw_flash_init | 1858.530s | 24193.144us | 3 | 3 | 100.00 | |
| chip_sw_flash_idle_low_power | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_idle_low_power | 317.080s | 3718.697us | 3 | 3 | 100.00 | |
| chip_sw_flash_keymgr_seeds | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2072.100s | 13009.886us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_creator_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 204.090s | 2614.322us | 0 | 3 | 0.00 | |
| chip_sw_flash_creator_seed_wipe_on_rma | 3 | 3 | 100.00 | |||
| chip_sw_flash_rma_unlocked | 5068.680s | 44565.426us | 3 | 3 | 100.00 | |
| chip_sw_flash_lc_owner_seed_sw_rw_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 204.090s | 2614.322us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 204.090s | 2614.322us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_iso_part_sw_wr_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 204.090s | 2614.322us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_seed_hw_rd_en | 0 | 3 | 0.00 | |||
| chip_sw_flash_ctrl_lc_rw_en | 204.090s | 2614.322us | 0 | 3 | 0.00 | |
| chip_sw_flash_lc_escalate_en | 94 | 100 | 94.00 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| chip_sw_flash_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 408.530s | 8832.904us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_clock_freqs | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_clock_freqs | 755.620s | 5640.617us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_escalation_reset | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 624.220s | 5024.967us | 3 | 3 | 100.00 | |
| chip_sw_flash_ctrl_write_clear | 3 | 3 | 100.00 | |||
| chip_sw_flash_crash_alert | 624.220s | 5024.967us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc | 6 | 6 | 100.00 | |||
| chip_sw_hmac_enc | 263.390s | 2889.204us | 3 | 3 | 100.00 | |
| chip_sw_hmac_enc_jitter_en | 288.300s | 3391.692us | 3 | 3 | 100.00 | |
| chip_sw_hmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_hmac_enc_idle | 275.520s | 3035.017us | 3 | 3 | 100.00 | |
| chip_sw_hmac_all_configurations | 3 | 3 | 100.00 | |||
| chip_sw_hmac_oneshot | 1431.550s | 8788.655us | 3 | 3 | 100.00 | |
| chip_sw_hmac_multistream_mode | 3 | 3 | 100.00 | |||
| chip_sw_hmac_multistream | 874.780s | 5069.619us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx | 9 | 9 | 100.00 | |||
| chip_sw_i2c_host_tx_rx | 636.230s | 5373.639us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx1 | 659.180s | 5551.451us | 3 | 3 | 100.00 | |
| chip_sw_i2c_host_tx_rx_idx2 | 553.750s | 4794.843us | 3 | 3 | 100.00 | |
| chip_sw_i2c_device_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_i2c_device_tx_rx | 408.310s | 3901.903us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 6 | 6 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2072.100s | 13009.886us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation_jitter_en | 1588.470s | 12125.046us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_kmac | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_kmac | 2228.400s | 11392.381us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_aes | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_aes | 1991.320s | 11661.139us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_sideload_otbn | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_sideload_otbn | 3575.550s | 14054.157us | 3 | 3 | 100.00 | |
| chip_sw_kmac_enc | 9 | 9 | 100.00 | |||
| chip_sw_kmac_mode_cshake | 206.170s | 2801.115us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac | 263.300s | 2974.337us | 3 | 3 | 100.00 | |
| chip_sw_kmac_mode_kmac_jitter_en | 259.370s | 3718.401us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_keymgr | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation | 2072.100s | 13009.886us | 3 | 3 | 100.00 | |
| chip_sw_kmac_app_lc | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_kmac_app_rom | 3 | 3 | 100.00 | |||
| chip_sw_kmac_app_rom | 208.210s | 3034.656us | 3 | 3 | 100.00 | |
| chip_sw_kmac_entropy | 3 | 3 | 100.00 | |||
| chip_sw_kmac_entropy | 1690.520s | 10400.785us | 3 | 3 | 100.00 | |
| chip_sw_kmac_idle | 3 | 3 | 100.00 | |||
| chip_sw_kmac_idle | 190.530s | 2678.456us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_alert_handler_escalation | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_escalation | 467.780s | 6236.794us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_jtag_access | 15 | 15 | 100.00 | |||
| chip_tap_straps_dev | 1268.240s | 14119.312us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 666.890s | 7762.701us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1500.650s | 16014.849us | 5 | 5 | 100.00 | |
| chip_sw_lc_ctrl_otp_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 266.320s | 3166.659us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_init | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_lc_ctrl_transitions | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_lc_ctrl_kmac_req | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_lc_ctrl_key_div | 3 | 3 | 100.00 | |||
| chip_sw_keymgr_key_derivation_prod | 2220.490s | 13094.412us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_broadcast | 74 | 84 | 88.10 | |||
| chip_sw_flash_ctrl_lc_rw_en | 204.090s | 2614.322us | 0 | 3 | 0.00 | |
| chip_sw_flash_rma_unlocked | 5068.680s | 44565.426us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 289.880s | 3227.192us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 762.370s | 6545.960us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 675.920s | 7504.546us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 748.430s | 6854.752us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_keymgr_key_derivation | 2072.100s | 13009.886us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 557.880s | 8938.575us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_execution_main | 700.960s | 8355.113us | 3 | 3 | 100.00 | |
| chip_prim_tl_access | 408.530s | 8832.904us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_lc | 951.050s | 15078.906us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 569.220s | 4614.830us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 557.690s | 4846.464us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 549.890s | 4037.680us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 543.390s | 4585.736us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 555.080s | 4479.056us | 3 | 3 | 100.00 | |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 540.290s | 5101.160us | 3 | 3 | 100.00 | |
| chip_tap_straps_dev | 1268.240s | 14119.312us | 5 | 5 | 100.00 | |
| chip_tap_straps_rma | 666.890s | 7762.701us | 5 | 5 | 100.00 | |
| chip_tap_straps_prod | 1500.650s | 16014.849us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 238.890s | 6933.689us | 0 | 3 | 0.00 | |
| chip_lc_scrap | 5 | 6 | 83.33 | |||
| chip_sw_lc_ctrl_rma_to_scrap | 232.740s | 4053.160us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_raw_to_scrap | 106.590s | 2911.195us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_test_locked0_to_scrap | 131.880s | 3244.633us | 1 | 1 | 100.00 | |
| chip_sw_lc_ctrl_rand_to_scrap | 233.920s | 3274.907us | 2 | 3 | 66.67 | |
| chip_lc_test_locked | 3 | 6 | 50.00 | |||
| chip_sw_lc_walkthrough_testunlocks | 2423.020s | 29813.373us | 3 | 3 | 100.00 | |
| chip_rv_dm_lc_disabled | 238.890s | 6933.689us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough | 6 | 15 | 40.00 | |||
| chip_sw_lc_walkthrough_dev | 904.490s | 11083.152us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prod | 905.680s | 10165.356us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_prodend | 981.650s | 9766.582us | 3 | 3 | 100.00 | |
| chip_sw_lc_walkthrough_rma | 631.030s | 6059.105us | 0 | 3 | 0.00 | |
| chip_sw_lc_walkthrough_testunlocks | 2423.020s | 29813.373us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock | 6 | 9 | 66.67 | |||
| chip_sw_lc_ctrl_volatile_raw_unlock | 150.600s | 3109.132us | 3 | 3 | 100.00 | |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 86.570s | 2031.931us | 3 | 3 | 100.00 | |
| rom_volatile_raw_unlock | 116.532s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_otbn_op | 6 | 6 | 100.00 | |||
| chip_sw_otbn_ecdsa_op_irq | 4714.190s | 17121.414us | 3 | 3 | 100.00 | |
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 5021.640s | 18897.032us | 3 | 3 | 100.00 | |
| chip_sw_otbn_rnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 801.540s | 6458.835us | 3 | 3 | 100.00 | |
| chip_sw_otbn_urnd_entropy | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 801.540s | 6458.835us | 3 | 3 | 100.00 | |
| chip_sw_otbn_idle | 3 | 3 | 100.00 | |||
| chip_sw_otbn_randomness | 801.540s | 6458.835us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 3 | 3 | 100.00 | |||
| chip_sw_otbn_mem_scramble | 437.720s | 4030.530us | 3 | 3 | 100.00 | |
| chip_otp_ctrl_init | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_otp_ctrl_keys | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1858.530s | 24193.144us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 437.720s | 4030.530us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2072.100s | 13009.886us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 550.540s | 5323.344us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 176.620s | 2325.420us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_entropy | 15 | 15 | 100.00 | |||
| chip_sw_flash_init | 1858.530s | 24193.144us | 3 | 3 | 100.00 | |
| chip_sw_otbn_mem_scramble | 437.720s | 4030.530us | 3 | 3 | 100.00 | |
| chip_sw_keymgr_key_derivation | 2072.100s | 13009.886us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access | 550.540s | 5323.344us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_invalidate | 176.620s | 2325.420us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_program | 14 | 15 | 93.33 | |||
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_sw_otp_ctrl_program_error | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_program_error | 425.460s | 4775.987us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_hw_cfg0 | 3 | 3 | 100.00 | |||
| chip_sw_lc_ctrl_otp_hw_cfg0 | 266.320s | 3166.659us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals | 26 | 30 | 86.67 | |||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 289.880s | 3227.192us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_dev | 762.370s | 6545.960us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_prod | 675.920s | 7504.546us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_lc_signals_rma | 748.430s | 6854.752us | 0 | 3 | 0.00 | |
| chip_sw_lc_ctrl_transition | 1212.120s | 33756.927us | 14 | 15 | 93.33 | |
| chip_prim_tl_access | 408.530s | 8832.904us | 3 | 3 | 100.00 | |
| chip_sw_otp_prim_tl_access | 3 | 3 | 100.00 | |||
| chip_prim_tl_access | 408.530s | 8832.904us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_dai_lock | 1 | 1 | 100.00 | |||
| chip_sw_otp_ctrl_dai_lock | 1032.460s | 7114.078us | 1 | 1 | 100.00 | |
| chip_sw_pwrmgr_external_full_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 293.500s | 5334.387us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_random_sleep_all_wake_ups | 1762.530s | 28326.412us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_wake_ups | 353.290s | 7511.005us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_por_reset | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_deep_sleep_por_reset | 523.610s | 7982.194us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_normal_sleep_por_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_por_reset | 515.920s | 6048.675us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_all_wake_ups | 1572.390s | 24482.167us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 2 | 6 | 33.33 | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 894.850s | 11000.477us | 0 | 3 | 0.00 | |
| chip_sw_aon_timer_wdog_bite_reset | 824.580s | 9044.719us | 2 | 3 | 66.67 | |
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 1294.390s | 12619.108us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_wdog_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_wdog_reset | 496.870s | 5558.566us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_aon_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_full_aon_reset | 293.500s | 5334.387us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_main_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_main_power_glitch_reset | 422.680s | 4273.953us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 2562.040s | 31455.839us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 465.020s | 6450.553us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_power_glitch_reset | 0 | 3 | 0.00 | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 196.050s | 3505.114us | 0 | 3 | 0.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 1 | 3 | 33.33 | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 2261.320s | 21089.566us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 947.120s | 9365.973us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_all_reset_reqs | 1506.020s | 10592.498us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_b2b_sleep_reset_req | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_b2b_sleep_reset_req | 2688.020s | 25991.939us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_disabled | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sleep_disabled | 257.510s | 3663.495us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_escalation_reset | 94 | 100 | 94.00 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| chip_sw_rom_access | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 557.880s | 8938.575us | 3 | 3 | 100.00 | |
| chip_sw_rom_ctrl_integrity_check | 3 | 3 | 100.00 | |||
| chip_sw_rom_ctrl_integrity_check | 557.880s | 8938.575us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_non_sys_reset_info | 10 | 12 | 83.33 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1506.020s | 10592.498us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 2261.320s | 21089.566us | 1 | 3 | 33.33 | |
| chip_sw_pwrmgr_wdog_reset | 496.870s | 5558.566us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_smoketest | 440.390s | 6477.837us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sys_reset_info | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 465.710s | 5082.408us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_cpu_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 532.960s | 7362.533us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_req_reset | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_req | 462.960s | 5575.434us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_alert_info | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_alert_info | 1728.510s | 12926.232us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_sw_rst | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_sw_rst | 226.360s | 3157.048us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_escalation_reset | 94 | 100 | 94.00 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| chip_sw_rstmgr_alert_handler_reset_enables | 3 | 3 | 100.00 | |||
| chip_sw_alert_handler_lpg_reset_toggle | 1486.710s | 8427.353us | 3 | 3 | 100.00 | |
| chip_sw_nmi_irq | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_nmi_irq | 700.660s | 5150.331us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_rnd | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_rnd | 690.010s | 4755.711us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_address_translation | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_address_translation | 208.090s | 3470.401us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_icache_scrambled_access | 3 | 3 | 100.00 | |||
| chip_sw_rv_core_ibex_icache_invalidate | 176.620s | 2325.420us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_fault_dump | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 532.960s | 7362.533us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_double_fault | 3 | 3 | 100.00 | |||
| chip_sw_rstmgr_cpu_info | 532.960s | 7362.533us | 3 | 3 | 100.00 | |
| chip_jtag_csr_rw | 3 | 3 | 100.00 | |||
| chip_jtag_csr_rw | 1731.040s | 17476.998us | 3 | 3 | 100.00 | |
| chip_jtag_mem_access | 3 | 3 | 100.00 | |||
| chip_jtag_mem_access | 1327.240s | 14080.853us | 3 | 3 | 100.00 | |
| chip_rv_dm_ndm_reset_req | 3 | 3 | 100.00 | |||
| chip_rv_dm_ndm_reset_req | 465.710s | 5082.408us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 0 | 3 | 0.00 | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 312.840s | 3459.211us | 0 | 3 | 0.00 | |
| chip_rv_dm_access_after_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_wakeup | 435.220s | 6714.604us | 3 | 3 | 100.00 | |
| chip_sw_rv_dm_jtag_tap_sel | 5 | 5 | 100.00 | |||
| chip_tap_straps_rma | 666.890s | 7762.701us | 5 | 5 | 100.00 | |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | |||
| chip_rv_dm_lc_disabled | 238.890s | 6933.689us | 0 | 3 | 0.00 | |
| chip_sw_plic_all_irqs | 9 | 9 | 100.00 | |||
| chip_plic_all_irqs_0 | 753.510s | 5656.631us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_10 | 367.660s | 3940.886us | 3 | 3 | 100.00 | |
| chip_plic_all_irqs_20 | 524.970s | 4766.265us | 3 | 3 | 100.00 | |
| chip_sw_plic_sw_irq | 3 | 3 | 100.00 | |||
| chip_sw_plic_sw_irq | 265.900s | 3523.588us | 3 | 3 | 100.00 | |
| chip_sw_timer | 3 | 3 | 100.00 | |||
| chip_sw_rv_timer_irq | 247.000s | 2665.842us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_flash_mode | 3 | 3 | 100.00 | |||
| rom_e2e_smoke | 4018.110s | 16725.689us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pass_through | 555.470s | 6179.582us | 3 | 3 | 100.00 | |
| chip_sw_spi_device_pass_through_collision | 0 | 3 | 0.00 | |||
| chip_sw_spi_device_pass_through_collision | 296.650s | 3952.282us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_tpm | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_tpm | 303.850s | 3252.979us | 3 | 3 | 100.00 | |
| chip_sw_spi_host_tx_rx | 3 | 3 | 100.00 | |||
| chip_sw_spi_host_tx_rx | 297.290s | 4001.967us | 3 | 3 | 100.00 | |
| chip_sw_sram_scrambled_access | 6 | 6 | 100.00 | |||
| chip_sw_sram_ctrl_scrambled_access | 550.540s | 5323.344us | 3 | 3 | 100.00 | |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 582.500s | 5906.566us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents | 6 | 6 | 100.00 | |||
| chip_sw_sleep_sram_ret_contents_no_scramble | 640.170s | 8821.686us | 3 | 3 | 100.00 | |
| chip_sw_sleep_sram_ret_contents_scramble | 499.850s | 7219.965us | 3 | 3 | 100.00 | |
| chip_sw_sram_execution | 3 | 3 | 100.00 | |||
| chip_sw_sram_ctrl_execution_main | 700.960s | 8355.113us | 3 | 3 | 100.00 | |
| chip_sw_sram_lc_escalation | 100 | 106 | 94.34 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| chip_sw_data_integrity_escalation | 703.030s | 6868.836us | 6 | 6 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 6 | 6 | 100.00 | |||
| chip_sw_pwrmgr_sysrst_ctrl_reset | 947.120s | 9365.973us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_reset | 1665.750s | 24822.999us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_inputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_inputs | 246.980s | 3563.528us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_outputs | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_outputs | 332.740s | 3934.181us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_in_irq | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_in_irq | 421.640s | 4113.297us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_wakeup | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1665.750s | 24822.999us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_sleep_reset | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_reset | 1665.750s | 24822.999us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ec_rst_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3454.460s | 20563.810us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_flash_wp_l | 3 | 3 | 100.00 | |||
| chip_sw_sysrst_ctrl_ec_rst_l | 3454.460s | 20563.810us | 3 | 3 | 100.00 | |
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 3 | 6 | 50.00 | |||
| chip_sw_sysrst_ctrl_ulp_z3_wakeup | 377.750s | 5055.785us | 3 | 3 | 100.00 | |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 3600.173s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_usbdev_vbus | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_vbus | 170.570s | 2756.673us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pullup | 222.900s | 2668.101us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_aon_pullup | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_aon_pullup | 346.110s | 4151.516us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_setup_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_setuprx | 511.220s | 4342.248us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_config_host | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_config_host | 1405.020s | 8880.726us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_pincfg | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_pincfg | 7106.820s | 31993.048us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_tx_rx | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_dpi | 2552.560s | 12728.217us | 1 | 1 | 100.00 | |
| chip_sw_usbdev_toggle_restore | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_toggle_restore | 257.540s | 2899.019us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_aes_masking_off | 3 | 3 | 100.00 | |||
| chip_sw_aes_masking_off | 295.390s | 3585.911us | 3 | 3 | 100.00 | |
| chip_sw_rv_core_ibex_lockstep_glitch | 2 | 3 | 66.67 | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 209.380s | 3004.960us | 2 | 3 | 66.67 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| chip_sw_coremark | 1 | 1 | 100.00 | |||
| chip_sw_coremark | 16570.120s | 71011.425us | 1 | 1 | 100.00 | |
| chip_sw_power_max_load | 3 | 3 | 100.00 | |||
| chip_sw_power_virus | 1554.820s | 6320.221us | 3 | 3 | 100.00 | |
| rom_e2e_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 230.020s | 4656.387us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 245.920s | 4604.088us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 300.590s | 4587.399us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_inject_test_unlocked0 | 279.510s | 4655.473us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_dev | 90.080s | 2100.124us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_inject_rma | 142.920s | 3193.015us | 0 | 1 | 0.00 | |
| rom_e2e_self_hash | 0 | 3 | 0.00 | |||
| rom_e2e_self_hash | 148.278s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_clkmgr_jitter_cycle_measurements | 0 | 3 | 0.00 | |||
| chip_sw_clkmgr_jitter_frequency | 405.690s | 3774.470us | 0 | 3 | 0.00 | |
| chip_sw_edn_boot_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_boot_mode | 380.650s | 2929.850us | 3 | 3 | 100.00 | |
| chip_sw_edn_auto_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_auto_mode | 1322.340s | 7150.775us | 3 | 3 | 100.00 | |
| chip_sw_edn_sw_mode | 3 | 3 | 100.00 | |||
| chip_sw_edn_sw_mode | 1755.090s | 10130.598us | 3 | 3 | 100.00 | |
| chip_sw_edn_kat | 3 | 3 | 100.00 | |||
| chip_sw_edn_kat | 294.150s | 2405.194us | 3 | 3 | 100.00 | |
| chip_sw_flash_memory_protection | 3 | 3 | 100.00 | |||
| chip_sw_flash_ctrl_mem_protection | 832.850s | 5648.663us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_vendor_test_csr_access | 3 | 3 | 100.00 | |||
| chip_sw_otp_ctrl_vendor_test_csr_access | 117.020s | 2912.808us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_escalation | 0 | 1 | 0.00 | |||
| chip_sw_otp_ctrl_escalation | 230.540s | 3226.943us | 0 | 1 | 0.00 | |
| chip_sw_sensor_ctrl_deep_sleep_wake_up | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 396.500s | 6181.005us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_usb_clk_disabled_when_active | 450.120s | 5736.331us | 3 | 3 | 100.00 | |
| chip_sw_all_resets | 3 | 3 | 100.00 | |||
| chip_sw_pwrmgr_all_reset_reqs | 1506.020s | 10592.498us | 3 | 3 | 100.00 | |
| chip_rv_dm_perform_debug | 0 | 3 | 0.00 | |||
| rom_e2e_jtag_debug_test_unlocked0 | 230.020s | 4656.387us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_dev | 245.920s | 4604.088us | 0 | 1 | 0.00 | |
| rom_e2e_jtag_debug_rma | 300.590s | 4587.399us | 0 | 1 | 0.00 | |
| chip_sw_rv_dm_access_after_hw_reset | 3 | 3 | 100.00 | |||
| chip_sw_rv_dm_access_after_escalation_reset | 532.430s | 6219.987us | 3 | 3 | 100.00 | |
| chip_sw_plic_alerts | 94 | 100 | 94.00 | |||
| chip_sw_all_escalation_resets | 682.110s | 5792.634us | 94 | 100 | 94.00 | |
| tick_configuration | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.167s | 0.000us | 0 | 3 | 0.00 | |
| counter_wrap | 0 | 3 | 0.00 | |||
| chip_sw_rv_timer_systick_test | 7200.167s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_spi_device_output_when_disabled_or_sleeping | 3 | 3 | 100.00 | |||
| chip_sw_spi_device_pinmux_sleep_retention | 272.220s | 3957.758us | 3 | 3 | 100.00 | |
| chip_sw_uart_watermarks | 5 | 5 | 100.00 | |||
| chip_sw_uart_tx_rx | 577.720s | 4269.874us | 5 | 5 | 100.00 | |
| chip_sw_usbdev_stream | 1 | 1 | 100.00 | |||
| chip_sw_usbdev_stream | 4050.220s | 18688.467us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 18 | 31 | 58.06 | |||
| chip_sival_flash_info_access | 310.060s | 3058.895us | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 26.570s | 10.340us | 0 | 3 | 0.00 | |
| chip_sw_otp_ctrl_rot_auth_config | 9.010s | 0.000us | 0 | 1 | 0.00 | |
| chip_sw_otp_ctrl_ecc_error_vendor_test | 200.780s | 2435.659us | 3 | 3 | 100.00 | |
| chip_sw_otp_ctrl_descrambling | 306.920s | 3319.688us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_lowpower_cancel | 360.490s | 3957.307us | 3 | 3 | 100.00 | |
| chip_sw_pwrmgr_sleep_wake_5_bug | 12.037s | 0.000us | 0 | 3 | 0.00 | |
| chip_sw_flash_ctrl_write_clear | 287.630s | 2792.273us | 3 | 3 | 100.00 | |
| ate_bootstrap_flash_erase | 888.850s | 10010.160us | 0 | 3 | 0.00 | |
| ate_bootstrap_one_frame | 9523.200s | 45450.782us | 3 | 3 | 100.00 | |
| ate_bootstrap_disjoint | 10800.171s | 0.000us | 0 | 3 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) | 90 test runs | |||
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 76515624418019868449052042956789717408825706249569262616005553848320479410407 | 308 |
UVM_INFO @ 3122.135460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 108947455890308050502289291367261647157859925017960912008609429080766206415241 | 308 |
UVM_INFO @ 3018.330973 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 23645497446940597759199854624540013877459816551287403463034815358459104578591 | 308 |
UVM_INFO @ 3005.134168 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 48291394613206153756090295782335392364213304116188101374328941991762817523688 | 308 |
UVM_INFO @ 3042.277771 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56111207043183495104548190419345361627095255488688874770794134365193176889885 | 308 |
UVM_INFO @ 2925.970229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97180779085838273469375882620281601628509026827382009805938676944105324012534 | 308 |
UVM_INFO @ 2682.935876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 33902282706496520270671284848172416245203191588058523689517058142336099211245 | 308 |
UVM_INFO @ 2672.108768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 85158376902666353290477603313541374168750296615264677075396408053898882159983 | 308 |
UVM_INFO @ 3101.894788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54013269371848912630645169642511487436112878698187623312803520343712434938003 | 308 |
UVM_INFO @ 3588.715570 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 114762644593244359650653940897991853073629766240391347826136391090917839383524 | 308 |
UVM_INFO @ 2955.366347 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 23658151435248291173757606967810925330310534175374184652607760587615499349146 | 308 |
UVM_INFO @ 2867.254400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7122684317373018674833924976713227907314183786685653494425799878973586001389 | 308 |
UVM_INFO @ 3345.513980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 34678744844396347860922214229917607118706998837259717379845733728793831257849 | 308 |
UVM_INFO @ 3640.531800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 113834804424513726904289540691149677479728271837875382312334211249497630884930 | 308 |
UVM_INFO @ 3131.031324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 35876294970491613216018352331144807174587884566544478455934260306038666470098 | 308 |
UVM_INFO @ 3642.263144 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 47202417370473482403435409887418498196591872625608947546140783573008049810804 | 308 |
UVM_INFO @ 2573.393460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 68916972526149141409465237441180226668271677980562843844309485383595795236345 | 308 |
UVM_INFO @ 3131.051016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 12517000421974104783180612336774039362887921997687031814397107957207219756009 | 308 |
UVM_INFO @ 2571.608945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 61935061279203937898231599059069511905279566756650612435573241756226017826328 | 308 |
UVM_INFO @ 3236.983800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 33102415307951998677090760542298202855989985392282126772066129515604398795680 | 308 |
UVM_INFO @ 3617.086651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 62058129748214106673311894725309623431629097734791283288460964181195298151574 | 308 |
UVM_INFO @ 2867.037314 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 13973409662916179333505433129850107619992872645535633478895673687532552164095 | 308 |
UVM_INFO @ 3619.586527 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 3128161384780924471983969124930860720018734884871104334059180723527215381649 | 308 |
UVM_INFO @ 2931.781390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 28714411224584563456920085072358374190311735402118770325479827883631495733944 | 308 |
UVM_INFO @ 2880.401779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50440290062400275712379081556495126776358475256092600745829496563850195900095 | 308 |
UVM_INFO @ 2959.145856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 56587642794961404251665099083842425044006382107506749723659294865949635175127 | 308 |
UVM_INFO @ 3396.440856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93773423067818648907117202832822848065643045091844073070013890241298931596288 | 308 |
UVM_INFO @ 2509.249576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 5240996078697980977112291572441333433713398207891996321576860708869494691974 | 308 |
UVM_INFO @ 3095.404986 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97234551428672619009357753825948459282984727228401125636026134400093288433336 | 308 |
UVM_INFO @ 3115.064807 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 55697476115415709183218642787791451574786414865365689308302521455510255950383 | 308 |
UVM_INFO @ 3094.212180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65943448150184222401176794042299586697686068840788677216377161799284971888146 | 308 |
UVM_INFO @ 2228.005080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 4560201962277279328665710013000508579936958314333319971222268872900268883928 | 308 |
UVM_INFO @ 3442.087448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 105796270357859112851825740398211897511451970042005232225191143756087885587833 | 308 |
UVM_INFO @ 3320.272458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 59367615290921655315737833874003856040918754350140958118859336593966819920579 | 308 |
UVM_INFO @ 3033.252289 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 24034792873582428261041580517608121173156593494009713494974584630270125113378 | 308 |
UVM_INFO @ 2778.398584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 64978758351646515190361611522931590379167427742803063060850356010618597638534 | 308 |
UVM_INFO @ 2905.666456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 74492511825658595677493972653478853144765958343531409256043566556149372238182 | 308 |
UVM_INFO @ 2145.398306 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15430272418904488331236097967107993474161610397088565867287183299917305168680 | 308 |
UVM_INFO @ 2569.447676 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 106482771888011916997438532110947099848255670456884046547141008848932619505177 | 308 |
UVM_INFO @ 2878.820960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 46154590492260902950870279402011012447328951045241403003804608576119956107657 | 308 |
UVM_INFO @ 2861.899906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 70008469669120086626797019491019173465192723715562154538557210840229412368119 | 308 |
UVM_INFO @ 2722.370232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54184115042069026918304658846009901042450394365196927127720112141131467474181 | 308 |
UVM_INFO @ 3205.162872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 85199923970063153714627282512766401094352498214519967415120595997249350327053 | 308 |
UVM_INFO @ 2771.444992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 113522231854030290265117455884484489762858529639001585608962347574353182181154 | 308 |
UVM_INFO @ 3516.053415 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 69875334509954067081997470220909806292367716035983954846999721842188849705377 | 308 |
UVM_INFO @ 3589.552940 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 27269230276390783808955999297615888580483974942576958715836806944425410769214 | 308 |
UVM_INFO @ 2840.857610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 26915603128762555527792030216151811077595224541705523357148878987916658616156 | 308 |
UVM_INFO @ 3723.491864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 65844668878907121794713973016393997706589513841457832142838033462932850642032 | 308 |
UVM_INFO @ 2684.651822 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30239288869126875409904255050345626583993221866651783817473968110563234799120 | 308 |
UVM_INFO @ 3293.751824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 42417511533607369776949803837738702871514993199667406937213008032566069967371 | 308 |
UVM_INFO @ 3031.329480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15669337349477370745005598011811135721476703439080343475430791555203688649960 | 308 |
UVM_INFO @ 2955.006846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 88903699300580089231227913409213518385414496269062746262653040308876578281549 | 308 |
UVM_INFO @ 2288.146298 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 71738867152709733949221906436458421675974351332080827975420537377588871454965 | 308 |
UVM_INFO @ 3249.904484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 62380374299181835536518950157107668512403644249214200580461523109374731733199 | 308 |
UVM_INFO @ 2891.325476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 16325337927577241655817989773004108143897369158556797160299020612527112971456 | 308 |
UVM_INFO @ 2448.481988 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 23857422388096702952473303892973100599489559078614377042593692183161741233439 | 308 |
UVM_INFO @ 2429.757865 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83211214636718754753166739667094079327518053890867848142484144757212055471755 | 308 |
UVM_INFO @ 3421.151672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54390793041648097583261850312858704540422896774305919807475781726927671098061 | 308 |
UVM_INFO @ 2745.399042 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 109838136240460271259492991719389693604886061106921554428583057761346591123593 | 308 |
UVM_INFO @ 3063.164746 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 20142482097709762186897516354304354492627489151133327836609933023481744767724 | 308 |
UVM_INFO @ 3299.329200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 26009116000446378485332138745719982777280364578136865816518463171221842929373 | 308 |
UVM_INFO @ 3268.330128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 89985203358910725671179787356165866469399147705829393377894510345101877819248 | 308 |
UVM_INFO @ 2852.808448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 112884202803312325219303028794702171685392488251942907369047802413067959623128 | 308 |
UVM_INFO @ 3187.573382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 30201125988533777873704989558570440451242596033008544564870616087191319738997 | 308 |
UVM_INFO @ 2735.353016 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 45798961099484085397416019326764737311871785128334725251533821473298624506578 | 308 |
UVM_INFO @ 3472.533184 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 62253603078487605530047959108667532170004455600409607443437343097951491114618 | 308 |
UVM_INFO @ 2555.572092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 25261830783877405757454220610265278252788927964910376804629343681171972155952 | 308 |
UVM_INFO @ 2621.749048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 416452134179386118199887214813296724187573051399085931514361177872881319537 | 308 |
UVM_INFO @ 3010.595544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54426765297259122952822970506595040874681826033295019676255498909794543003689 | 308 |
UVM_INFO @ 2715.129218 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 111608790571444726324151585642601547458141331112524410466187799606821479882485 | 308 |
UVM_INFO @ 3043.840220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 87926469130859227536225959526333129220190824109883592167672538745698649321329 | 308 |
UVM_INFO @ 2472.021704 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 47095562754679380158237557947504293581009036104241402018986540900800962927580 | 308 |
UVM_INFO @ 2698.886458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 90336328404296201927754855688084619217005731254258320962985436742078838437820 | 308 |
UVM_INFO @ 2969.248356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 7059111671263891174485712725306848907952671382807053471324827226151775227767 | 308 |
UVM_INFO @ 3414.300358 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 80126804563904023955908702159264657648439899697064520833780384176247061529411 | 308 |
UVM_INFO @ 3306.888558 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 49455719828341365248859541922055513534606330107857474203059772181066671718601 | 308 |
UVM_INFO @ 3053.339336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 66475491569444122700425442998423198085673911792635688491623679435173845557225 | 308 |
UVM_INFO @ 2915.846598 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 50427653486373047534742162647734643694170541022249067601874388808381946614155 | 308 |
UVM_INFO @ 2778.019276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83083110686471039737766086321537882499428035117361819165876173708933129079042 | 308 |
UVM_INFO @ 3069.601665 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 21114752649396697328610250929750384160796512918490711639136236195974165075100 | 308 |
UVM_INFO @ 2733.218816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 54175969978127344051714052759690315715190915103202686445311795934038903796942 | 308 |
UVM_INFO @ 2851.181398 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 93540588712333988448768650232893312872887887520701972941423117376866118002765 | 308 |
UVM_INFO @ 2800.450800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 15591638459345643156818299903174056968599500373953776121066991426527733025275 | 308 |
UVM_INFO @ 2654.855140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 110173795554432675367283731484243705549415087597447949138497276479985650999206 | 308 |
UVM_INFO @ 2911.310700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 83191740972578913119511147881453684453609358006587270729608500338831969222818 | 308 |
UVM_INFO @ 3130.353880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 2873017806668613887116244793636201136568096644761231554040760083965223094878 | 308 |
UVM_INFO @ 2600.253741 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 22426980083780049316254296176310364755190569452363545206564160202520180784677 | 308 |
UVM_INFO @ 2729.394574 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 109439488940182533613500259282213940187711115586916750336241274290945824528722 | 308 |
UVM_INFO @ 3671.729604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 97093893137224729169823438335618583739344701774383846524805738493606658479841 | 308 |
UVM_INFO @ 3170.249844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_alert_handler_lpg_sleep_mode_alerts | 14059581830498761197262778413681113578893055706448629498763431873556559905658 | 308 |
UVM_INFO @ 2485.538152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 42 test runs | |||
| chip_sw_pwrmgr_sleep_wake_5_bug | 91151349086260970053899947915266926500542229470573284469168251418151393687925 | None |
---- STDERR ----
Another command (pid=2784131) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=2787678) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 7170897087109028215347960758648777853531425973459725245587852893199640629092 | None |
Another command (pid=310352) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=308545) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=311252) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 23575443429072129044201405020268204646846197684088538020970794289031201668122 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 607831825459726945030541449068536925556455722711716786299606847925138882770 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 45269900379154290625817725266084014386913906870968471772087185796967773232486 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 7075983288133804727116989262157058581777136825209422081540401720020466213196 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 56162097942251642818251453802773400830652036520493976086136825652858200108410 | None |
Another command (pid=311781) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=285413) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=310352) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 77988304490319500388596851004129560382363519575730116836638507282120679728551 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 114130786527523890763302809393583231946562661665616237397707071613472880022540 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 87186139033996541501706390368222631736418441245611059118503542745770062050597 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 89183407617366539432528389156085450932611258336499993769472474104264838612018 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 12857818319107979714891585967238787837838309190739377913475387035040298459913 | None |
Another command (pid=287142) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=309102) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=318915) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 7381142834757806298425081968446984324134564828704119746512972164014449620679 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 7069246641526893727700761727134771448295123812760541744260314247152691313922 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 100831282846137106246885113302141738860464172217265294886948821029485739504566 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 15918308966032359599681893909100217405407316563195377787401958767112145284201 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 102001108216199788425569004001141685773385558321289059200645138349337003038423 | None |
Another command (pid=283370) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=284531) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=280661) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 114835115553664795785428356808213951681576959927013534421984465339206129755890 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 64333316609710818111759991105120653022886593242734240445678233471882985423560 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 81761760489155940172649910251599361470338631166577988970948490158026038667159 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 36023654813067740354927309712009811519428325109234058892169350482333835175748 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 19777495885225577062269343673266910032537820816274969791138082431341230413962 | None |
Another command (pid=286704) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=309745) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=296098) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 110818770878707677763312847983694399369560130673648415615842930431784328601940 | None |
Another command (pid=383001) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=391500) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=388222) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 110646513915691930650907492310371796492524685188401816298928918390190797650215 | None |
Another command (pid=320573) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=287612) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=323481) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 4726320636071069421467056144155695437325643889068449109618357263786569306887 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 7911424180631663067657163511128003538628345525380119934790679210972813250938 | None |
Another command (pid=307430) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=311593) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=311781) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 84092529458585337580551606585291757554900338220630131352081443510966600541987 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 64386065596235049216444480953507641463454628673396220585554121880476411571959 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 38562599043975494272909295827149515199534764565436751713991607497149477673588 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 107426876372225303581896323283353299239160287902638955596462859248801040261966 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 46587258338240955778859242923288578482912342342058987427984479770625635264647 | None |
Another command (pid=325056) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=323481) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=324806) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 104624271320397228511964609646249257583568216304904468401349984913257461132108 | None |
Another command (pid=372523) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=365713) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=364484) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 103749876995234813965856266685756145490180456198978712242470963538465901526345 | None |
Another command (pid=280661) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=283721) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=287874) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| chip_sw_pwrmgr_sleep_wake_5_bug | 97273515490164316336505465356179752700494852367254184410303055829080229889309 | None |
---- STDERR ----
Another command (pid=486607) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_test_unlocked0 | 16161037969590483328076134609456689110882048384809266261248917437865431069255 | None |
Another command (pid=370790) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=369490) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=372523) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_dev | 99250497118095916237422997251033102269742849056863378793400330462063498824617 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod | 53084558713817820367599313791992587329817813241497123703256477179914312319714 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_prod_end | 106403224210665788903563972940241218940800855559403967107547213304411411224875 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_asm_init_rma | 88431536892265185965576582913464082622295728342972064678278738403769198346061 | None |
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_volatile_raw_unlock | 97920820616778979265505936599155660314812108692334620863390750122792663947142 | None |
Another command (pid=320573) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=316734) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=323481) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_raw_unlock | 52640841946876963222320570048098700445106837765048498209491226293520758135698 | None |
Another command (pid=307430) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=311593) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=311781) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| rom_e2e_self_hash | 58733016436485071491856148632778232025990120058235603056040336271269019529860 | None |
---- STDERR ----
Another command (pid=287874) is running. Waiting for it to complete on the server (server_pid=280291)...
Another command (pid=288301) is running. Waiting for it to complete on the server (server_pid=280291)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
|
|
| UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). | 37 test runs | |||
| chip_tl_errors | 46594050206617841203935803972273442632421222126071212622221532940796009577966 | 217 |
TL item was: req: (cip_tl_seq_item@32028) { a_addr: 'h10764 a_data: 'h57771b8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h1a50c d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2463.221352 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 52411162030307606719556363291276678067806449315214671048555742320985765161623 | 242 |
TL item was: req: (cip_tl_seq_item@213032) { a_addr: 'h10760 a_data: 'ha6fec02f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h1a981 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 6086.061048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 25326652884631046652072058502675991293342336263947340138230336468493463396636 | 217 |
TL item was: req: (cip_tl_seq_item@32740) { a_addr: 'h10694 a_data: 'h655fef8c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2e a_opcode: 'h4 a_user: 'h18646 d_param: 'h0 d_source: 'h2e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2191.545604 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 57238642064927815180273309589815491661897163431614928550938566933871940357390 | 224 |
TL item was: req: (cip_tl_seq_item@32050) { a_addr: 'h10658 a_data: 'h58a75d5a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h14 a_opcode: 'h4 a_user: 'h18672 d_param: 'h0 d_source: 'h14 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3127.441612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 57412974267170761023238303372316490281891598727261067676711265669039602243956 | 224 |
TL item was: req: (cip_tl_seq_item@32166) { a_addr: 'h107e4 a_data: 'h5e4233a5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h6 a_opcode: 'h4 a_user: 'h195e3 d_param: 'h0 d_source: 'h6 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2406.524775 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 56927167369763803724400618677647817849837952780956163916344263995297705397018 | 224 |
TL item was: req: (cip_tl_seq_item@31850) { a_addr: 'h1035c a_data: 'h7aeaaf54 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h19e91 d_param: 'h0 d_source: 'h29 d_data: 'h100073 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd04 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2869.374679 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 31622384570116413587130836552652280567811942381947960304846807943271812704250 | 217 |
TL item was: req: (cip_tl_seq_item@35616) { a_addr: 'h106dc a_data: 'hed6fffda a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h1ba6a d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1902.926120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 56409690586276985739992913896874812950892961357338234940059969427355801866194 | 217 |
TL item was: req: (cip_tl_seq_item@37516) { a_addr: 'h107d4 a_data: 'h6badeae4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1a992 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2094.742146 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 37239186372292161775291370457661351511344859583061085171963529478494594960560 | 224 |
TL item was: req: (cip_tl_seq_item@31610) { a_addr: 'h107a8 a_data: 'hc3db95bd a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h27 a_opcode: 'h4 a_user: 'h1a531 d_param: 'h0 d_source: 'h27 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2698.012510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 83958603507036811235941523581846747665660244322305169027894649843063893434158 | 217 |
TL item was: req: (cip_tl_seq_item@39858) { a_addr: 'h104f4 a_data: 'h8c26416 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h1bd3e d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2151.997894 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 70004752067090044592961372163820887671703626411532915753645798781999337721587 | 224 |
TL item was: req: (cip_tl_seq_item@32298) { a_addr: 'h10740 a_data: 'he310c26 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h1b148 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2334.499060 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 42552416397490725770550782807330959448084419878371649464516031304171072478942 | 217 |
TL item was: req: (cip_tl_seq_item@37430) { a_addr: 'h104c0 a_data: 'hd2301237 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h12 a_opcode: 'h4 a_user: 'h18db5 d_param: 'h0 d_source: 'h12 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2002.722100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 37907008722829025360401731550631391728810359324284435372439114940341934909914 | 224 |
TL item was: req: (cip_tl_seq_item@31910) { a_addr: 'h10100 a_data: 'h703c20f4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h181ad d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2027.254045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 93384255842893219548492143318801878012625957839411794826709502451864738956311 | 217 |
TL item was: req: (cip_tl_seq_item@35274) { a_addr: 'h10340 a_data: 'h9728085f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h9 a_opcode: 'h4 a_user: 'h1a223 d_param: 'h0 d_source: 'h9 d_data: 'hc55513 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd33 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2733.095980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 3744130233454792651184179640004763651347615396264712798047597069617411190018 | 217 |
TL item was: req: (cip_tl_seq_item@32814) { a_addr: 'h105bc a_data: 'h3c0f774d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h23 a_opcode: 'h4 a_user: 'h18646 d_param: 'h0 d_source: 'h23 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2436.473906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 64353945326447704007633638112909618881117186444077948596055094434379299173451 | 224 |
TL item was: req: (cip_tl_seq_item@31696) { a_addr: 'h106c4 a_data: 'h6b9ab8e1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h18a11 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2246.278877 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 72737768967725972475474198233083816798150053297219330443995482952073610231078 | 217 |
TL item was: req: (cip_tl_seq_item@31858) { a_addr: 'h10554 a_data: 'h9e6b8a67 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1920e d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1830.352200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 13390386592470238154421460066907208651359032808188480846216091197347160671849 | 224 |
TL item was: req: (cip_tl_seq_item@33128) { a_addr: 'h1056c a_data: 'hb5907a51 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'ha a_opcode: 'h4 a_user: 'h1baf4 d_param: 'h0 d_source: 'ha d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2261.601408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 90481617176238770273027745033283232547874885008935730791640162552858986886184 | 217 |
TL item was: req: (cip_tl_seq_item@32890) { a_addr: 'h10338 a_data: 'h6b14ac05 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1a221 d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2181.906026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 60754980446762456639270497110064360954147039374011128246213918371316874012299 | 218 |
TL item was: req: (cip_tl_seq_item@179518) { a_addr: 'h10544 a_data: 'h34443552 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2c a_opcode: 'h4 a_user: 'h1b6b7 d_param: 'h0 d_source: 'h2c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2973.077432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 12617892577032947039099014232034540340064641871751532640251087023244516621662 | 242 |
TL item was: req: (cip_tl_seq_item@211572) { a_addr: 'h10524 a_data: 'h27496b23 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h186a4 d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 5933.581984 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 33887622000839702179911727292282770139028229558443357892329305988630163861895 | 217 |
TL item was: req: (cip_tl_seq_item@32088) { a_addr: 'h1073c a_data: 'hc633d92 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h16 a_opcode: 'h4 a_user: 'h1bde1 d_param: 'h0 d_source: 'h16 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2424.743691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 90059627447990239189870127948843373871582685686774231763344303576041102825931 | 217 |
TL item was: req: (cip_tl_seq_item@32026) { a_addr: 'h106a4 a_data: 'h259be41b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h1ba3d d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2028.854950 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 49016070217987426652429036661638653050656713896601371633245831157018506510376 | 224 |
TL item was: req: (cip_tl_seq_item@31520) { a_addr: 'h10400 a_data: 'hca8b37f7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h24 a_opcode: 'h4 a_user: 'h1958d d_param: 'h0 d_source: 'h24 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2056.702085 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 79323438057222002716427880962408535147385147639084637006701247644976447579292 | 217 |
TL item was: req: (cip_tl_seq_item@34266) { a_addr: 'h105e4 a_data: 'hb42fe788 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'hf a_opcode: 'h4 a_user: 'h19eb0 d_param: 'h0 d_source: 'hf d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2622.779264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 60216040472881081111910545726387856565926051212437386947415691458468854869571 | 217 |
TL item was: req: (cip_tl_seq_item@37794) { a_addr: 'h105ec a_data: 'h6f24af4b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h18 a_opcode: 'h4 a_user: 'h18a1c d_param: 'h0 d_source: 'h18 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2812.382392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 19111892741532257130332738939871704913692932887158135269458300785571279058170 | 217 |
TL item was: req: (cip_tl_seq_item@43468) { a_addr: 'h105bc a_data: 'h2fa3f72b a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h29 a_opcode: 'h4 a_user: 'h18601 d_param: 'h0 d_source: 'h29 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3121.257137 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_csr_mem_rw_with_rand_reset | 75180763033792801678397845846584158358731934195210305747030055482461287850668 | 224 |
TL item was: req: (cip_tl_seq_item@31940) { a_addr: 'h107bc a_data: 'h3f18246f a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h18d08 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2368.916373 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 79352262995670802291059038261079463469179792427569549243064617999362997822805 | 217 |
TL item was: req: (cip_tl_seq_item@33838) { a_addr: 'h106fc a_data: 'haefab807 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1f a_opcode: 'h4 a_user: 'h1a2e2 d_param: 'h0 d_source: 'h1f d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2316.655188 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 106959299974104912301197976886337647731460607441560261049067437734836948932011 | 217 |
TL item was: req: (cip_tl_seq_item@31456) { a_addr: 'h10644 a_data: 'h7ad39d44 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3b a_opcode: 'h4 a_user: 'h1baa1 d_param: 'h0 d_source: 'h3b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2651.091536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 84677139714775716987991967912871380237019244932184743927380921842780902609118 | 217 |
TL item was: req: (cip_tl_seq_item@32264) { a_addr: 'h10510 a_data: 'hab8b6cb3 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1d a_opcode: 'h4 a_user: 'h1b61c d_param: 'h0 d_source: 'h1d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2318.512337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 64539072054598446565492183809631822620121127152064205120055395089734873512715 | 217 |
TL item was: req: (cip_tl_seq_item@31436) { a_addr: 'h1078c a_data: 'h47467918 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h17 a_opcode: 'h4 a_user: 'h1b110 d_param: 'h0 d_source: 'h17 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2566.257106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 79138707198324119197877990839201112066615286937033808745488563971471247711205 | 217 |
TL item was: req: (cip_tl_seq_item@32628) { a_addr: 'h1071c a_data: 'hc01f6cdb a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h39 a_opcode: 'h4 a_user: 'h1a524 d_param: 'h0 d_source: 'h39 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2042.995148 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 11982218867590586145693701083381275734924472504237270128341908565070898791573 | 217 |
TL item was: req: (cip_tl_seq_item@31426) { a_addr: 'h106b0 a_data: 'h4247a0e8 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2a a_opcode: 'h4 a_user: 'h1921c d_param: 'h0 d_source: 'h2a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 3020.448355 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 47882634872864552629141478640673266655547305359824496354434218484818395832922 | 217 |
TL item was: req: (cip_tl_seq_item@33422) { a_addr: 'h10650 a_data: 'h82dee847 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1c a_opcode: 'h4 a_user: 'h192b2 d_param: 'h0 d_source: 'h1c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2663.204797 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 86210493009842750645884582330937767232273505117691528930354841221344573611716 | 217 |
TL item was: req: (cip_tl_seq_item@33314) { a_addr: 'h107f8 a_data: 'h67cca83 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3e a_opcode: 'h4 a_user: 'h1a97a d_param: 'h0 d_source: 'h3e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2556.834026 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_tl_errors | 73804988585863418596036368205339470339919039030301447683555757808763374633420 | 217 |
TL item was: req: (cip_tl_seq_item@34344) { a_addr: 'h10700 a_data: 'heb36c41a a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h19 a_opcode: 'h4 a_user: 'h199a0 d_param: 'h0 d_source: 'h19 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2450.808910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job timed out after * minutes | 12 test runs | |||
| chip_sw_rv_timer_systick_test | 50802125702050381375653903474547105693358810801716552874463549543055871265387 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 26268961891574132673088143480098930876528678603147359249824714092738598051888 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 17727118767727422526521826032961296733019657107372722075768681130058996087527 | None | ||
| ate_bootstrap_disjoint | 45718912451415160875942665429415453525358085764294069832249079732971205982606 | None | ||
| chip_sw_rv_timer_systick_test | 98857485638834273827373961555539338518119538961257291760663726365086780675164 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 59891798864515245992368642560734023443721381907919520840030440710025816274583 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 54049605842836610302917467531759922582475244108791087176867253076592818194658 | None | ||
| ate_bootstrap_disjoint | 43265407669349210992746005879141694739596499156633811389206943983457823935028 | None | ||
| chip_sw_rv_timer_systick_test | 64521957592593665673581389433250336942868946814903656773227818099360050180824 | None | ||
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 7495578452252594039792571880017359039487048665527879317595670489158803368758 | None | ||
| chip_sw_alert_handler_lpg_sleep_mode_pings | 56558842363006030976042312434718234126021951995545109564599256535584501370235 | None | ||
| ate_bootstrap_disjoint | 74194393191353813344940309719168844493722488045283567846820518251537099886635 | None | ||
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 9 test runs | |||
| chip_sw_lc_walkthrough_dev | 87136196639755655779221789261888884820476378863412871875082354466122848713286 | 369 |
UVM_INFO @ 11083.151660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 64615142904341733714705536618992547604289254869627106774056269946620933167318 | 369 |
UVM_INFO @ 10136.033910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 63504917472455541494853652090727675969584238295232511731734688694650908565210 | 341 |
UVM_INFO @ 7372.636933 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 28412101238028821580749050381609445706678162505811336544208996257418805431309 | 369 |
UVM_INFO @ 9635.724882 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 65029252558206216397016139996497704937818990968128506698249175100979568496105 | 369 |
UVM_INFO @ 12546.913810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 106561037107947855353558010874286802264907289777123289287987719734345188256369 | 341 |
UVM_INFO @ 6059.104919 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_dev | 20681386681835675392830043548425561559113861665557994876970366510412014631671 | 369 |
UVM_INFO @ 9440.707120 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_prod | 29381584880825399122565853594425826505116085009698282731932391614681849723951 | 369 |
UVM_INFO @ 10165.356357 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_lc_walkthrough_rma | 26609130369005698433991035523245439814174243087356962675841941124545152013493 | 341 |
UVM_INFO @ 6994.054852 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Error-[NOA] Null object access | 9 test runs | |||
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 30783244172606930606249340323324293204658909854709852957287088889840514961916 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_test_unlocked0 | 49920027509483367967863536749873819841163061468836547937953895707921916501402 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_dev | 76435020612635301018592771704984831906768985665684548335029551157955348923742 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_debug_rma | 6414352340405706307527837024564763385356649478494329570026753285387721556656 | 319 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_test_unlocked0 | 40616482053796331791753469856188920617153979658830229825648381992096714131759 | 310 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_dev | 77106826423437764002142126506292181169282710645530014262418717927079791906672 | 305 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| rom_e2e_jtag_inject_rma | 111340588987235126791856409796592866017953434216470678622715328478544480144472 | 305 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 29983157630412401786685065765244852597586290619157058952365186793843557807435 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 21065852381467273693874144245782628716948149613264418066494577225644496646557 | 327 |
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
|
|
| Offending '(rstreqs[*] && (reset_cause == HwReq))' | 8 test runs | |||
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 111121786797756438221674447062653589629736805894079268944919341699192151165085 | 344 |
UVM_ERROR @ 12601.865000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 12601.865000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 68244953704606798977862536116036966947154332285536786301120857042732815160162 | 327 |
UVM_ERROR @ 9888.941500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9888.941500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 66253879611247648403813600002025544089334316285849303037509840648714530224904 | 325 |
UVM_ERROR @ 6890.314000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6890.314000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 19239523971689161718930992057012634141535692049697264323615020116352919581161 | 315 |
UVM_ERROR @ 5909.220000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5909.220000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 105240633089594408469000620168404319318015036654157591468445140894421559645114 | 314 |
UVM_ERROR @ 5417.580000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5417.580000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_deep_sleep_por_reset | 113029099008298710551335143220836645196270509731796124355772192319202752243661 | 325 |
UVM_ERROR @ 7982.194000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7982.194000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_aon_timer_wdog_bite_reset | 79148297766193400609805053615043808535643063646661721485274520518919741923141 | 319 |
UVM_ERROR @ 7856.797000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7856.797000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 47864725829996241579982311308679039020613630139827476895738310711136695977480 | 316 |
UVM_ERROR @ 5512.377000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 5512.377000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' | 6 test runs | |||
| chip_sw_otp_ctrl_escalation | 110280671763051631118783638636358178581482086437494474474896567979810344182857 | 316 |
UVM_ERROR @ 3226.942808 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3226.942808 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 25265377470803836622370308504853952181910890192017760429306156605201130451467 | 312 |
UVM_ERROR @ 3205.172584 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3205.172584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 27261421451854797798566581192919851442768322733614339558957291941893816690785 | 312 |
UVM_ERROR @ 3480.056784 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3480.056784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_csrng_fuse_en_sw_app_read_test | 24053835298390603002210835099585401020693775887551869742984094549614371175022 | 312 |
UVM_ERROR @ 2890.840044 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2890.840044 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 23126261698622765340173420194865766040504747080672174282241839208318579748243 | 317 |
UVM_ERROR @ 3329.818430 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3329.818430 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 81857188044076868858821494402972175140722518591093364138841599658009618068266 | 317 |
UVM_ERROR @ 3470.410994 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3470.410994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 6 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 102047591757872281015765046037431394113391906879218600050522095160534772137615 | 368 |
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 105375779535999189766455295208696596170537881896138986224633445824446739862513 | 368 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 50729924412585048060560026919747370542331234522759490150647044568647235109240 | 368 |
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 51676602114845179882227504439581177347971930895677099373228183139154827855598 | 328 |
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 104555716179799690001553500825517280599711807099891745322302554563334359654512 | 328 |
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 36375404580858285039792907901823629137206142214916704734242405593520181239405 | 328 |
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '((~rst_ni) === (~seed_en_q))' | 4 test runs | |||
| chip_sw_lc_ctrl_rand_to_scrap | 20815938919908454725972218742051993188753069964851724006858469670130725964616 | 318 |
UVM_ERROR @ 3470.600000 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 3470.600000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 72294619762450441960924215353518132669088993426374932373723789908081861885793 | 320 |
UVM_ERROR @ 6431.376750 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 6431.376750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 106142853816399454263481790968126040188466222564932207890404396000266025046783 | 303 |
UVM_ERROR @ 2158.997740 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 2158.997740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_full_aon_reset | 111952725371751263035029988575668215844862925384181779656847847078339703308087 | 320 |
UVM_ERROR @ 5334.387350 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5334.387350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' | 4 test runs | |||
| chip_sw_pwrmgr_sleep_power_glitch_reset | 105973234371305122401863788427121832542401171707067329171285031244127419676017 | 313 |
UVM_ERROR @ 2572.721356 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2572.721356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_random_sleep_power_glitch_reset | 79101214662283584330232731735615125071111921357171344929749718951549432229005 | 405 |
UVM_ERROR @ 20735.914092 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 20735.914092 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 90984982347796038959065178615954439266435414979823223033371348892440650190964 | 313 |
UVM_ERROR @ 2833.880960 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 2833.880960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_pwrmgr_sleep_power_glitch_reset | 38530832005827458648816810734147950317975919432938708054520064495861903449825 | 313 |
UVM_ERROR @ 3505.113760 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3505.113760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr_aon.u_d0_spi_host*.leaf_rst_path | 3 test runs | |||
| chip_sw_rstmgr_rst_cnsty_escalation | 13905020202811943909719886014518316616435886378770485233084900154641884949907 | 301 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 110138220298775651661705781309035316240658748677830763040067937606203496665920 | 301 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_rstmgr_rst_cnsty_escalation | 9962884811857036749903459320663930610223322085892960182423276358946654235186 | 301 |
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_flash_ctrl_lc_rw_en | 105346319542059677302852575241235491511160026366229560139583805987806577716445 | 309 |
UVM_INFO @ 3385.799672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 75878619910426368935642426964279405409462921373151676844178636556458754453898 | 309 |
UVM_INFO @ 3077.629417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_flash_ctrl_lc_rw_en | 107937473468895733947412130944240852048254481285667579045258607203343688086599 | 309 |
UVM_INFO @ 2614.322153 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * | 3 test runs | |||
| chip_sw_otp_ctrl_lc_signals_rma | 64885318911639910924606753533380457957975340806544293059278676996242364821122 | 342 |
UVM_INFO @ 5865.916750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 100032885970561299378719747982498078640778882549570485235345497519788399440593 | 342 |
UVM_INFO @ 6854.751860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_otp_ctrl_lc_signals_rma | 8388542392747381537813601899702307635810632903682851726432722742659917983163 | 342 |
UVM_INFO @ 6121.151045 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected | 3 test runs | |||
| chip_sw_clkmgr_jitter_frequency | 69162969571292205680651911667668415575955804490269850021086458785716268276519 | 343 |
UVM_INFO @ 3774.469586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 35570801727836987172073129079775093003287746761776579467687824861853861212299 | 343 |
UVM_INFO @ 3970.470274 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_clkmgr_jitter_frequency | 113878532198883370100613845825903671761031833181417956550945492811413670197243 | 343 |
UVM_INFO @ 3161.012471 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 3 test runs | |||
| chip_rv_dm_lc_disabled | 11458745402357522817693974803474883977428227284596581579278062370330445343307 | 215 |
UVM_INFO @ 2315.330649 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 11662176754926240618077957853683487503175084988859774842528693371132973094295 | 245 |
UVM_INFO @ 6933.688905 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_rv_dm_lc_disabled | 110976716372607259955072252357922906304837413680195350899194802582241882763907 | 235 |
UVM_INFO @ 4895.037189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_idle_load | 91811922683819160733919718401567659726092740332830742588063136594077809595085 | 312 |
UVM_INFO @ 3293.939000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 49895618946312776841467409108199325535196272635537958614591649529448275712859 | 312 |
UVM_INFO @ 3287.479000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_idle_load | 114387834779766156275895175587264258603840668768370870514276246602689022416221 | 312 |
UVM_INFO @ 2931.711000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * | 3 test runs | |||
| chip_sw_power_sleep_load | 9063736557003686447612192307804949411573937403630727529196589935368048956575 | 318 |
UVM_INFO @ 2996.116000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 46411414768833319291587708307101987084690347104831402802994957067464483359272 | 318 |
UVM_INFO @ 2977.080500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_power_sleep_load | 113923337927086088231899512711819933786864422876313457024878947835272152004612 | 318 |
UVM_INFO @ 3760.324000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * | 3 test runs | |||
| chip_sw_ast_clk_rst_inputs | 78826084997877089792392070671386222126769361505278091117324518143289261469602 | 327 |
UVM_INFO @ 15797.372483 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 37648128122218579015790034445753314295429522111769509485686205375655945792439 | 327 |
UVM_INFO @ 15967.318094 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_ast_clk_rst_inputs | 74236724061330338898959014784174336669273714153247499055990999002923654061228 | 327 |
UVM_INFO @ 15073.290915 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) | 3 test runs | |||
| ate_bootstrap_flash_erase | 2119218499306881661833305747731903087949474714553163095772067152188519507213 | 272 |
UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 107712106740167667674563940059166184106011577718436947408092596876440500757875 | 272 |
UVM_INFO @ 10010.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ate_bootstrap_flash_erase | 49338958595701684905881867377436969346449331999654100450950159855772108401966 | 272 |
UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode | 3 test runs | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 113302445465685968745619326988665497354620889792106573221578994750016478419692 | 328 |
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 7315701644113185065448239617195254450458540836893703376563704752736361446675 | 328 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 46525588326899141316016010378380420268735888194337452837651685564903233454011 | 328 |
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '$stable(key_data_i)' | 3 test runs | |||
| rom_keymgr_functest | 68106534982888338731623406894370426447690499711383126029044372919867093954948 | 327 |
UVM_ERROR @ 5911.396280 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5911.396280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 82379523002764661986515800245607861179693843951039431414720186624941319254392 | 327 |
UVM_ERROR @ 5227.891223 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5227.891223 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_keymgr_functest | 94417053108316555389321522098081938887764054699677221152517727584925226253202 | 327 |
UVM_ERROR @ 5139.379064 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5139.379064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(reset_cause == HwReq)' | 2 test runs | |||
| chip_sw_sensor_ctrl_alert | 85185834241045696313307058433534959440753908523558144692011308801903416296204 | 316 |
UVM_ERROR @ 2978.393484 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2978.393484 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_sensor_ctrl_alert | 113496437918239948839702247762508236348957265234164870854344340570337809181653 | 316 |
UVM_ERROR @ 3695.115384 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 3695.115384 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 75112159813263546743381137161321823406508295843754549106911893176562935257362 | 365 |
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 86301741565456334087680495360182768835720368355482836877571494843924784119152 | 325 |
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 2 test runs | |||
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 21054180545592869104638857616165742075798612278174976576598984873872108593800 | 368 |
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 43994153793168500750427656223815289491093407736540160690790156855245078684768 | 326 |
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty | 2 test runs | |||
| chip_sw_spi_device_pass_through_collision | 82669443160239243071406582407458203270532995033927249430626845824912945237296 | 327 |
UVM_INFO @ 3857.510288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_spi_device_pass_through_collision | 58861276917885738821021573722492322190501107398410514764659640597354613612305 | 327 |
UVM_INFO @ 3952.281520 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got * | 2 test runs | |||
| chip_sw_all_escalation_resets | 40990924920129837884884062105784870312959403444925307073131095961884667035997 | 317 |
UVM_INFO @ 2874.206820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 6397345858889803673476136380355086370593946705722346435216331188317574290111 | 317 |
UVM_INFO @ 3296.962470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (cip_base_vseq.sv:923) virtual_sequencer [chip_sw_all_escalation_resets_vseq] Alert usbdev_fatal_fault fired unexpectedly. | 2 test runs | |||
| chip_sw_all_escalation_resets | 40787978561641485386192541547394481274416931240195371968766584630883082818402 | 316 |
UVM_INFO @ 2866.918824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| chip_sw_all_escalation_resets | 18812630327437500731882842821435483460965691039701645944885949891410131055888 | 316 |
UVM_INFO @ 3127.908632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch | 1 test run | |||
| chip_sw_spi_device_pass_through_collision | 27850341052651268394562988802207572132758250441048810434002825548715858538850 | 329 |
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode | 1 test run | |||
| chip_sw_otp_ctrl_rot_auth_config | 39373783590004498239183121919008921468277410524410258843061608460600521503215 | 282 |
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 86557884227653763878536818554776234134065372782386429286405835879075506467793 | 307 |
UVM_INFO @ 3697.309721 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 55500543056777344489107198080286619840568300810419633828323723507403431375030 | 325 |
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode | 1 test run | |||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 74674250308505464605344017370288532433934925995026297024806915887090006150345 | 328 |
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 101010568940763625354843645957191813022352282939733231533237777382143611616361 | 307 |
UVM_INFO @ 2933.571048 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. | 1 test run | |||
| chip_sw_rv_core_ibex_lockstep_glitch | 103592968614185868140501400058046875200830043560954284527276765436794333527801 | 327 |
UVM_INFO @ 3004.959930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * | 1 test run | |||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 38725468692856942697843565197412185143994406338097148395390465794408843370910 | 319 |
UVM_INFO @ 15454.547875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Offending '(pend_req[h2d.a_source].pend == *)' | 1 test run | |||
| chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 99783200821589020707446925336459550019070326028104186686136104732098427791936 | 341 |
UVM_ERROR @ 11000.476752 us: (tlul_assert.sv:314) [ASSERT FAILED] pendingReqPerSrc_M
UVM_INFO @ 11000.476752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *! | 1 test run | |||
| chip_sw_alert_test | 36217781467879153251757735513998834984631306589894634191100785917773318720327 | 307 |
UVM_INFO @ 3425.550890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched! | 1 test run | |||
| chip_sw_lc_ctrl_transition | 5008080903584450583002721488172403126288945645013580278568193601714865243206 | 347 |
UVM_INFO @ 33756.927388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|