Simulation Results: clkmgr

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.92 %
  • code
  • 98.70 %
  • assert
  • 95.76 %
  • func
  • 87.31 %
  • line
  • 99.16 %
  • branch
  • 98.95 %
  • cond
  • 96.18 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.72%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
clkmgr_smoke 1.540s 85.914us 50 50 100.00
csr_hw_reset 5 5 100.00
clkmgr_csr_hw_reset 1.210s 43.391us 5 5 100.00
csr_rw 20 20 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
csr_bit_bash 5 5 100.00
clkmgr_csr_bit_bash 11.520s 3338.332us 5 5 100.00
csr_aliasing 5 5 100.00
clkmgr_csr_aliasing 2.420s 136.884us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
clkmgr_csr_mem_rw_with_rand_reset 2.230s 152.496us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
clkmgr_csr_aliasing 2.420s 136.884us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 50 50 100.00
clkmgr_peri 1.320s 151.520us 50 50 100.00
trans_enables 50 50 100.00
clkmgr_trans 2.130s 462.410us 50 50 100.00
extclk 50 50 100.00
clkmgr_extclk 1.860s 230.782us 50 50 100.00
clk_status 50 50 100.00
clkmgr_clk_status 1.370s 88.903us 50 50 100.00
jitter 50 50 100.00
clkmgr_smoke 1.540s 85.914us 50 50 100.00
frequency 50 50 100.00
clkmgr_frequency 18.010s 2358.266us 50 50 100.00
frequency_timeout 50 50 100.00
clkmgr_frequency_timeout 20.160s 2301.726us 50 50 100.00
frequency_overflow 50 50 100.00
clkmgr_frequency 18.010s 2358.266us 50 50 100.00
stress_all 50 50 100.00
clkmgr_stress_all 91.200s 10568.905us 50 50 100.00
alert_test 50 50 100.00
clkmgr_alert_test 1.500s 130.702us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
clkmgr_tl_errors 6.670s 842.176us 20 20 100.00
tl_d_illegal_access 20 20 100.00
clkmgr_tl_errors 6.670s 842.176us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
clkmgr_csr_hw_reset 1.210s 43.391us 5 5 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
clkmgr_csr_aliasing 2.420s 136.884us 5 5 100.00
clkmgr_same_csr_outstanding 2.950s 407.308us 20 20 100.00
tl_d_partial_access 50 50 100.00
clkmgr_csr_hw_reset 1.210s 43.391us 5 5 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
clkmgr_csr_aliasing 2.420s 136.884us 5 5 100.00
clkmgr_same_csr_outstanding 2.950s 407.308us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 10 25 40.00
clkmgr_sec_cm 36.730s 10041.050us 0 5 0.00
clkmgr_tl_intg_err 59.840s 10023.170us 10 20 50.00
shadow_reg_update_error 13 20 65.00
clkmgr_shadow_reg_errors 1023.710s 200000.000us 13 20 65.00
shadow_reg_read_clear_staged_value 13 20 65.00
clkmgr_shadow_reg_errors 1023.710s 200000.000us 13 20 65.00
shadow_reg_storage_error 13 20 65.00
clkmgr_shadow_reg_errors 1023.710s 200000.000us 13 20 65.00
shadowed_reset_glitch 13 20 65.00
clkmgr_shadow_reg_errors 1023.710s 200000.000us 13 20 65.00
shadow_reg_update_error_with_csr_rw 9 20 45.00
clkmgr_shadow_reg_errors_with_csr_rw 1078.150s 200000.000us 9 20 45.00
sec_cm_bus_integrity 10 20 50.00
clkmgr_tl_intg_err 59.840s 10023.170us 10 20 50.00
sec_cm_meas_clk_bkgn_chk 50 50 100.00
clkmgr_frequency 18.010s 2358.266us 50 50 100.00
sec_cm_timeout_clk_bkgn_chk 50 50 100.00
clkmgr_frequency_timeout 20.160s 2301.726us 50 50 100.00
sec_cm_meas_config_shadow 13 20 65.00
clkmgr_shadow_reg_errors 1023.710s 200000.000us 13 20 65.00
sec_cm_idle_intersig_mubi 50 50 100.00
clkmgr_idle_intersig_mubi 1.850s 143.712us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 50 50 100.00
clkmgr_lc_ctrl_intersig_mubi 1.540s 91.314us 50 50 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 50 50 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.520s 116.174us 50 50 100.00
sec_cm_clk_handshake_intersig_mubi 47 50 94.00
clkmgr_clk_handshake_intersig_mubi 1.710s 250.738us 47 50 94.00
sec_cm_div_intersig_mubi 50 50 100.00
clkmgr_div_intersig_mubi 1.420s 88.103us 50 50 100.00
sec_cm_jitter_config_mubi 20 20 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 36.730s 10041.050us 0 5 0.00
sec_cm_meas_config_regwen 20 20 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
sec_cm_clk_ctrl_config_regwen 20 20 100.00
clkmgr_csr_rw 1.540s 252.627us 20 20 100.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 36.730s 10041.050us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 50 50 100.00
clkmgr_regwen 7.800s 1045.455us 50 50 100.00
stress_all_with_rand_reset 50 50 100.00
clkmgr_stress_all_with_rand_reset 119.140s 18451.505us 50 50 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 12 test runs
clkmgr_shadow_reg_errors 102905546291109072566302894133297194431177939166459670639682553140189898981699 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 76995538445054115314657711702118764716998549834837012533915706331122775916797 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 95292557143897593453270986288196139778387449352323629124264900999777083610852 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 31018368039365898715420055687986798959138436153005936998659574640551512757390 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 24363792380659458308409995861699032006016517517812908783900817160545859095390 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 85004426652593715846414484839830288588102919514597329168083425584120175226067 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 157934102505716424550825262856282518205223522746517466563882203913121499655 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 26289866200204262698259518189174339407294466106292268395678738745349829333896 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 78264518772986238120505486771124496819438377778302941366722640194462738331312 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 36844120948999741060916505357267144066261436020971252711926501093811681279582 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors 42466540826010443904059801377623716077341369672908991062063799261793219910763 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 107578246081000530083569612495883781451502099449336627292326571142553761013390 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 12 test runs
clkmgr_tl_intg_err 34746624784150533621205138354771133233510083466948523152924770417989209284022 174
UVM_INFO @ 10049128491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 74089730490559274694457947672575142546477564819969097315998345004318988306357 94
UVM_INFO @ 10023170114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 112171948477320750540284729583094870243466310634076471391066263488283401529517 85
UVM_INFO @ 10025611752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 94758156340053967649289019773771143059778972256603841018302232820846448203833 101
UVM_INFO @ 10035107487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 16552622687113281057770408253129413911934834378852241683948136527489840114012 102
UVM_INFO @ 10041049883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 48805483644354738977151768345852230671302693016527042321454002386181965626707 153
UVM_INFO @ 10126265685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 11242722914637641271279118967920255055715691605778427423350691996384065171772 116
UVM_INFO @ 10035285922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 17722485112880281921357164547856445837502098544272065626511390038670131431006 111
UVM_INFO @ 10080265558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 28770851306015693571938933059048964697556230988395853753518842587347445388859 199
UVM_INFO @ 10135388577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 43945089146302567064333963290502412791827111086946481971588192959386611781456 86
UVM_INFO @ 10023853268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 57319986874873167422923120436423869767278631652999608056511347470602747426139 119
UVM_INFO @ 10024417317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 104570581824342946423819974198695865979051933546268995867276367154254601960186 147
UVM_INFO @ 10167458102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 4 test runs
clkmgr_shadow_reg_errors_with_csr_rw 113667043037281379524981138849587469972377909126322394887387970328725123955317 75
UVM_INFO @ 38481622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 29868612956513247767172914741289626869366179228203170377010205236761868350547 75
UVM_INFO @ 30759940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 45872609804749982519550060599423123951183511455210029800396001937010034514445 75
UVM_INFO @ 72566310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_shadow_reg_errors_with_csr_rw 71271935366987845809924151823794740856618156712424479145859821222621111490205 76
UVM_INFO @ 84270109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 3 test runs
clkmgr_sec_cm 103492562945346062390529844736834507150173093121525565445975394732406210592568 77
UVM_INFO @ 3027713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 51978696084672382822796470206331244657203629685665599991642787298427967874090 80
UVM_INFO @ 6439066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_sec_cm 105798792673864415870781336568715492602203147826990819185144835954429526675985 87
UVM_INFO @ 15540746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_extclk_vseq.sv:99) [clkmgr_extclk_vseq] Check failed exp_all_clk_byp_ack == rd_data (* [*] vs * [*]) extclk_status mismatch 3 test runs
clkmgr_clk_handshake_intersig_mubi 99542438689171102527434071955987195778358309823797200224875391654609428735714 74
UVM_INFO @ 194086632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 81337394368415502473214295950152274978986327500555975149508789091109711756731 74
UVM_INFO @ 5250414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_clk_handshake_intersig_mubi 33615175145145837000295145935196283773815197302692704618827887079273482442894 74
UVM_INFO @ 16973943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 38553752218762101442649607494162049699455688857665046888427884212457314902214 76
UVM_INFO @ 2243605630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:215) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_regwen (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 93296156517521386527554157575419766932105830057272619039378593183833528207218 75
UVM_INFO @ 2039018429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---