Simulation Results: csrng

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.73 %
  • code
  • 96.17 %
  • assert
  • 97.16 %
  • func
  • 90.86 %
  • block
  • 98.49 %
  • line
  • 99.50 %
  • branch
  • 96.30 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
97.07%
V2S
97.70%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
csrng_smoke 34.000s 84.900us 50 50 100.00
csr_hw_reset 5 5 100.00
csrng_csr_hw_reset 34.000s 110.486us 5 5 100.00
csr_rw 20 20 100.00
csrng_csr_rw 36.000s 317.142us 20 20 100.00
csr_bit_bash 5 5 100.00
csrng_csr_bit_bash 52.000s 831.156us 5 5 100.00
csr_aliasing 5 5 100.00
csrng_csr_aliasing 39.000s 464.794us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
csrng_csr_mem_rw_with_rand_reset 35.000s 223.195us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
csrng_csr_rw 36.000s 317.142us 20 20 100.00
csrng_csr_aliasing 39.000s 464.794us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
alerts 500 500 100.00
csrng_alert 65.000s 5947.186us 500 500 100.00
err 500 500 100.00
csrng_err 34.000s 19.493us 500 500 100.00
cmds 9 50 18.00
csrng_cmds 287.000s 28545.220us 9 50 18.00
life cycle 9 50 18.00
csrng_cmds 287.000s 28545.220us 9 50 18.00
stress_all 48 50 96.00
csrng_stress_all 1196.000s 62879.932us 48 50 96.00
intr_test 50 50 100.00
csrng_intr_test 33.000s 12.838us 50 50 100.00
alert_test 50 50 100.00
csrng_alert_test 33.000s 22.102us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
csrng_tl_errors 34.000s 97.434us 20 20 100.00
tl_d_illegal_access 20 20 100.00
csrng_tl_errors 34.000s 97.434us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
csrng_csr_hw_reset 34.000s 110.486us 5 5 100.00
csrng_csr_rw 36.000s 317.142us 20 20 100.00
csrng_csr_aliasing 39.000s 464.794us 5 5 100.00
csrng_same_csr_outstanding 34.000s 100.867us 20 20 100.00
tl_d_partial_access 50 50 100.00
csrng_csr_hw_reset 34.000s 110.486us 5 5 100.00
csrng_csr_rw 36.000s 317.142us 20 20 100.00
csrng_csr_aliasing 39.000s 464.794us 5 5 100.00
csrng_same_csr_outstanding 34.000s 100.867us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
csrng_tl_intg_err 35.000s 86.951us 20 20 100.00
sec_cm_config_regwen 41 70 58.57
csrng_regwen 33.000s 2.762us 21 50 42.00
csrng_csr_rw 36.000s 317.142us 20 20 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 65.000s 5947.186us 500 500 100.00
sec_cm_intersig_mubi 48 50 96.00
csrng_stress_all 1196.000s 62879.932us 48 50 96.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 65.000s 5947.186us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
sec_cm_constants_lc_gated 48 50 96.00
csrng_stress_all 1196.000s 62879.932us 48 50 96.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 65.000s 5947.186us 500 500 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
csrng_tl_intg_err 35.000s 86.951us 20 20 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
csrng_sec_cm 52.000s 634.689us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 42.000s 572.353us 200 200 100.00
csrng_err 34.000s 19.493us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 10802.047s 0.000us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 38 test runs
csrng_cmds 68081125460317478854918720126625679653442815860553161264195073005003069372137 100
UVM_INFO @ 191120755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 45051257623137018507843768579779339380502989405030174212882540023773869877455 100
UVM_INFO @ 109905411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 25170051023162481631594383722903290369021921238128975403457030183411434593590 100
UVM_INFO @ 28171542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 112236764919725268501233277952077279754539883748227062182737716091235050941568 100
UVM_INFO @ 56664704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 33950969228947019384845684081741052677276504059468078682284037724341995082028 100
UVM_INFO @ 157281705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103415943424270732437476100797719701667559694955474917882175686146926175495449 100
UVM_INFO @ 89199559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 54588747558333092724733449025628428123529526454681273243767337140016369724358 109
UVM_INFO @ 62510741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 65029636282970500836930051866243285864770144369060834656529520246381873808547 100
UVM_INFO @ 95245496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103933145253397862685538553431885489357725585634728981068105181428439879247904 100
UVM_INFO @ 178157560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 90517289078841888989730684811334186269475190836862107503813553917253213835387 100
UVM_INFO @ 224005057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 24481335856822714903231613126943304640440655905687306917554437466938396866827 110
UVM_INFO @ 253074278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 100482176687999101010688900684507776271234926238315623791583228845907554384640 100
UVM_INFO @ 152023959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 27168973014012055893842144161255684058117606624130491155119839967445523862413 110
UVM_INFO @ 227708619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 81693756323733391717085589742434526003532986562463582259686320174727565981455 100
UVM_INFO @ 364982069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 36989988496445012729310410997585741160013284693373637156796451767124838075634 100
UVM_INFO @ 276291345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23222378392932270760680280499444585201707950660762704935729679210106553991075 100
UVM_INFO @ 96143767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 48329742534137792122706717939974139545239465740433403835135918159818141474895 110
UVM_INFO @ 374586846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 30421347028078716969349499075714339911184032542127335900349163737949333900542 100
UVM_INFO @ 98257017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 111869880904701157353253815086669476891451462283322873762012313824069437589845 100
UVM_INFO @ 259505677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 103448147697206626663231247759272984393581521204574290686926421432171679638092 100
UVM_INFO @ 119688080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 66246868138028669497903794422592558890859586752719726237997318512520613857700 100
UVM_INFO @ 92432226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 87802795626868760770826363358777391724872097814957209632650552266216254333106 100
UVM_INFO @ 75699165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 6942414259320378625946675543243504086401596867142778849915661184990800634496 100
UVM_INFO @ 73672187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 32282282940487484865477889532251214407558725642283839116559271078972713345470 100
UVM_INFO @ 190425842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 110370539317854728876281220258671141283546077011882972772135022645658065124581 100
UVM_INFO @ 180661084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 26583077974597648558027695350005177119772715565452895706857286335188107800420 100
UVM_INFO @ 523196062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 109792324679016373286234427235979506404008337469302019650287928280118646855906 100
UVM_INFO @ 488893015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 94895701099633747935234529398408942054817521362093088323048808580766193777574 100
UVM_INFO @ 83716943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 45807994522290170358144344569164320025993771892856352766752780497343988858384 100
UVM_INFO @ 100916613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 41247329192868053571657763189208451691329410039551262654326622905864968961455 100
UVM_INFO @ 28927721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 75657103765652711038971748982041596407129107795822590626606941317372095735920 100
UVM_INFO @ 567966703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 67574477842049831643123976802274963184215921213586983724833067840453121528490 130
UVM_INFO @ 616325574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 104044615959643145145967103327971679900686895590483849266059682846253304454240 100
UVM_INFO @ 444563582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 93014980042747591786798343574276409245662216097414401623596860187591743632065 100
UVM_INFO @ 11330409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 84287326902087978658909375796124199852719288460204719931259835075241898981779 100
UVM_INFO @ 99457821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 31453542974448432069066723937265326318381755304665314654496720873263323391868 100
UVM_INFO @ 32238601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 23594091949961219015394783488725207172234967951880307460881216214380394670715 100
UVM_INFO @ 26430337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 77074965830788927715415734394833468410469541823703205972454190186388394621566 100
UVM_INFO @ 87851211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 23 test runs
csrng_regwen 59836703801531459959476963494746460051570943330613483561523818361978846121984 99
UVM_INFO @ 2761814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 99303545007306771454709799522287942660077052358304561952156819199276761872898 99
UVM_INFO @ 2580735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 19844149224150371381067045227842315930356407148264949588860643470665773784937 99
UVM_INFO @ 4492202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 58640059226779849084257399180963887525410282096729266536988873892808478879090 99
UVM_INFO @ 24374545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 29531271070045723473421643754974915728658898392826689595661529422838320948380 99
UVM_INFO @ 10419654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 30849501936671316572753026207141310645165240982768715649510560179559345732453 99
UVM_INFO @ 10521272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 68665857144243887172022948746590508152198026602797908567340803155728297081323 99
UVM_INFO @ 2658636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 64300142639317889547754047644836689162636238035960553222049993477689607689903 99
UVM_INFO @ 5993996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 91315884970947131277999759971772060952605226766682777210130741602148422754304 99
UVM_INFO @ 28635151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 81642059354631660179697937394393742886494848944155163301508063473572213081229 99
UVM_INFO @ 14497197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 14048332714184894141546303844528308432320632023442300543552846090592875148764 99
UVM_INFO @ 10893853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 33301803245181946629356756662871462371277174916102663577094866015209619659821 99
UVM_INFO @ 2280405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 60968294155333694662794863650602446195445650495814942922578778120421307961320 99
UVM_INFO @ 11340934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 108018485000625109479722236580175755419597265186449374255814171760370129543201 99
UVM_INFO @ 2687545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 66889090550536434490707679407891731332174493265888401753900306109108388256365 99
UVM_INFO @ 14126618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 3319552712946095422737833569381402297485237320855922747900257481391168253719 99
UVM_INFO @ 19950869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 6546862014112556866645219487772420811282370802773798967103298448582678682102 99
UVM_INFO @ 11054664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 96510432250348077432888314007624392870203451190911945242518161087280585017500 99
UVM_INFO @ 2985609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 63767561508033229338849930594843380547208879395109035491413588258526166352270 99
UVM_INFO @ 2737141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 25610084568756436726068773143358938499233857628247156378733939049517443678479 99
UVM_INFO @ 2933571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 111443944362283540969969430135840288865762341782557489253371626658115843388674 99
UVM_INFO @ 12864954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 109305037075099171599114501378835184100556934411913185578065334930227150654847 99
UVM_INFO @ 27652780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 57139590870785852788688675665625867662663877350628284129437131093403903066990 99
UVM_INFO @ 1577150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 6 test runs
csrng_regwen 60455140971252522635591544589667072877261668047657329480885970152971976728170 99
UVM_INFO @ 2919818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 14913945402036079877615613372119811978935816109455222843489968133827790064789 99
UVM_INFO @ 5586061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 82780623426424269897331506812325859977436441417125795630351855066526708072754 99
UVM_INFO @ 6925324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 110771040593756122337121483482353029361671470342874998874196944299280538538245 99
UVM_INFO @ 6143725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 38600151104604450483117833508685810023957030409687540672093647344662245831617 99
UVM_INFO @ 5851728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_regwen 100818882224528347162688535773752620933291883707293018944631962430034089142713 99
UVM_INFO @ 4041568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 5 test runs
csrng_stress_all_with_rand_reset 85922989790740993258537569771352258725189042509068813283600502658484222803073 159
UVM_INFO @ 488538964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 8628184712996168799429200018209776986604070628855475137318578444003178370643 128
UVM_INFO @ 5381467790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 19493069373852388993237132947671626135471357489721971510810335016661587414589 153
UVM_INFO @ 919509438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 54023503678430403448525452217919308322086570382135894431231594821848208522918 111
UVM_INFO @ 116045059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 19391228709121985411239064677824952824288393699525972650159824874535468381311 122
UVM_INFO @ 6292806783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 4 test runs
csrng_stress_all_with_rand_reset 5329237131623990495424131716011553586416590248387582515085307979577550162970 None
csrng_stress_all_with_rand_reset 1793480784324837517234767056542692415111373981707338539711135651198873402102 None
csrng_stress_all_with_rand_reset 113008081019416671186710405355482860887299281485889283386884669580209131827423 None
csrng_stress_all_with_rand_reset 55728251966730082199501222339710875302077752123207353853155109705983342448043 None
UVM_ERROR (csrng_scoreboard.sv:429) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: csrng_reg_block.genbits 2 test runs
csrng_cmds 9753191512771997035379629622759699232085350901697857298986920662363437153640 103
UVM_INFO @ 97460273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_cmds 91985142788096803042809529205492324312321488200104303156326623012827135916794 113
UVM_INFO @ 1143797770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 61715565249269195485131880196841062442778215410349508825225329656950051992119 135
UVM_INFO @ 1458321464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_env_cfg.sv:358) [cfg] Check failed hw_v == * (* [*] vs * [*]) 1 test run
csrng_stress_all_with_rand_reset 49616692420085919804577623168814838257457102289414661297584941997799904471808 123
UVM_INFO @ 1182164587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:268) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_alert triggered unexpectedly 1 test run
csrng_cmds 96077177577134018109306176592901997070336166806210513932510752344845548855413 108
UVM_INFO @ 14869754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---