Simulation Results: edn/edn0

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.72 %
  • code
  • 95.58 %
  • assert
  • 98.92 %
  • func
  • 92.66 %
  • line
  • 98.91 %
  • branch
  • 96.51 %
  • cond
  • 93.96 %
  • toggle
  • 97.12 %
  • FSM
  • 91.40 %
Validation stages
V1
100.00%
V2
98.87%
V2S
100.00%
V3
92.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.010s 18.689us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 1.280s 48.694us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 1.080s 16.283us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 3.140s 256.868us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.690s 62.264us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.440s 32.167us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 1.080s 16.283us 20 20 100.00
edn_csr_aliasing 1.690s 62.264us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 47.700s 2238.135us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 47.700s 2238.135us 300 300 100.00
genbits 300 300 100.00
edn_genbits 47.700s 2238.135us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.050s 22.914us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.420s 52.725us 200 200 100.00
errs 100 100 100.00
edn_err 1.220s 30.057us 100 100 100.00
disable 89 100 89.00
edn_disable 1.110s 15.679us 50 50 100.00
edn_disable_auto_req_mode 14.190s 500.000us 39 50 78.00
stress_all 50 50 100.00
edn_stress_all 8.670s 386.038us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 0.990s 22.895us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.160s 25.156us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.420s 141.015us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.420s 141.015us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 1.280s 48.694us 5 5 100.00
edn_csr_rw 1.080s 16.283us 20 20 100.00
edn_csr_aliasing 1.690s 62.264us 5 5 100.00
edn_same_csr_outstanding 1.390s 225.602us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 1.280s 48.694us 5 5 100.00
edn_csr_rw 1.080s 16.283us 20 20 100.00
edn_csr_aliasing 1.690s 62.264us 5 5 100.00
edn_same_csr_outstanding 1.390s 225.602us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 6.690s 2512.938us 5 5 100.00
edn_tl_intg_err 2.320s 142.534us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 1.090s 116.061us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.420s 52.725us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.690s 2512.938us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 6.690s 2512.938us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 6.690s 2512.938us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 6.690s 2512.938us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.420s 52.725us 200 200 100.00
edn_sec_cm 6.690s 2512.938us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.420s 52.725us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 2.320s 142.534us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 46 50 92.00
edn_stress_all_with_rand_reset 107.350s 11011.223us 46 50 92.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 8 test runs
edn_disable_auto_req_mode 77212679472147181317282693226849818354177524380702520478168414821277125334729 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 109753647962458181397304852669415359870652629093947951204348215691432208041835 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 2134115805686360078173837110178752740251472979464241756178494621896837644444 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 33807381463977010239068327650042151912208537555425236750320811138786608233347 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 39157156671472895803018143000333101184973893485821276245658059128272256699088 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 442935446923209064367919581539231174177903752871120939542226960289469994670 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 68942997611581862533671808390641096106964421794358315500874871709018895539299 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 51509865557943183822150287315675988915911500199638332032073283750932564299043 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 82733076112350654486557386953677235553551291496752015752458819451311286373909 88
UVM_INFO @ 33234474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 72213897946138858448711863524845317261586719345887907802376769755921035246269 88
UVM_INFO @ 40374653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 3574568979956529317986770578577078410438560303435319233812372063889311454381 88
UVM_INFO @ 81240207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 3 test runs
edn_stress_all_with_rand_reset 35348261059920948728481412406409914968689789842927273234647134894458856552810 135
UVM_INFO @ 235141586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 41768787432220686523519860596918250992911539971897110493726939286281941400335 163
UVM_INFO @ 1041515176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 37626345574141350784788960455240257726782142704985874877619776275928500186872 234
UVM_INFO @ 1545848732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. 1 test run
edn_stress_all_with_rand_reset 63201545405158825605974768407193536065220476241060747558163588127146156773657 123
UVM_INFO @ 439325850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---