Simulation Results: edn/edn1

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.55 %
  • code
  • 95.93 %
  • assert
  • 98.70 %
  • func
  • 92.02 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
98.76%
V2S
100.00%
V3
88.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
edn_smoke 1.070s 23.197us 50 50 100.00
csr_hw_reset 5 5 100.00
edn_csr_hw_reset 0.910s 16.943us 5 5 100.00
csr_rw 20 20 100.00
edn_csr_rw 0.890s 43.823us 20 20 100.00
csr_bit_bash 5 5 100.00
edn_csr_bit_bash 4.350s 700.947us 5 5 100.00
csr_aliasing 5 5 100.00
edn_csr_aliasing 1.140s 80.002us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
edn_csr_mem_rw_with_rand_reset 1.460s 157.635us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
edn_csr_rw 0.890s 43.823us 20 20 100.00
edn_csr_aliasing 1.140s 80.002us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 300 300 100.00
edn_genbits 153.310s 19893.720us 300 300 100.00
csrng_commands 300 300 100.00
edn_genbits 153.310s 19893.720us 300 300 100.00
genbits 300 300 100.00
edn_genbits 153.310s 19893.720us 300 300 100.00
interrupts 50 50 100.00
edn_intr 1.180s 31.355us 50 50 100.00
alerts 200 200 100.00
edn_alert 1.430s 411.234us 200 200 100.00
errs 100 100 100.00
edn_err 1.150s 27.948us 100 100 100.00
disable 88 100 88.00
edn_disable 1.090s 12.570us 50 50 100.00
edn_disable_auto_req_mode 13.670s 500.000us 38 50 76.00
stress_all 50 50 100.00
edn_stress_all 6.220s 319.223us 50 50 100.00
intr_test 50 50 100.00
edn_intr_test 1.070s 41.561us 50 50 100.00
alert_test 50 50 100.00
edn_alert_test 1.150s 113.050us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
edn_tl_errors 3.230s 826.738us 20 20 100.00
tl_d_illegal_access 20 20 100.00
edn_tl_errors 3.230s 826.738us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
edn_csr_hw_reset 0.910s 16.943us 5 5 100.00
edn_csr_rw 0.890s 43.823us 20 20 100.00
edn_csr_aliasing 1.140s 80.002us 5 5 100.00
edn_same_csr_outstanding 1.210s 64.361us 20 20 100.00
tl_d_partial_access 50 50 100.00
edn_csr_hw_reset 0.910s 16.943us 5 5 100.00
edn_csr_rw 0.890s 43.823us 20 20 100.00
edn_csr_aliasing 1.140s 80.002us 5 5 100.00
edn_same_csr_outstanding 1.210s 64.361us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
edn_sec_cm 3.750s 393.305us 5 5 100.00
edn_tl_intg_err 8.510s 944.847us 20 20 100.00
sec_cm_config_regwen 10 10 100.00
edn_regwen 0.900s 20.219us 10 10 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.430s 411.234us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.750s 393.305us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 3.750s 393.305us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 3.750s 393.305us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 3.750s 393.305us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.430s 411.234us 200 200 100.00
edn_sec_cm 3.750s 393.305us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.430s 411.234us 200 200 100.00
sec_cm_tile_link_bus_integrity 20 20 100.00
edn_tl_intg_err 8.510s 944.847us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 44 50 88.00
edn_stress_all_with_rand_reset 98.860s 20629.593us 44 50 88.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 8 test runs
edn_disable_auto_req_mode 57609738330756658611021749675463477730118102494896501601793981318328292889882 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 40245288607826993519140924371206985360447379569704699293682928589469728220013 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 1440481996712905109983200583805751124679654916741363334465728473949600445084 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 16026930314084354437604064273681350901579946019178021798910697392867567443675 89
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 47043476126757906104294407839278057548528677090102525724473139585423732710442 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 63037942998971075786709369364827523706769279120265155598530370298318265565895 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 69909570775200981048787071848789348749261532479548705159690552219478934355827 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 15243541932806754468453783403294671153878167954411270245061738626190555896067 88
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
edn_stress_all_with_rand_reset 46421168204929532291419409988694633336739540773559196999446966638383783738180 183
UVM_INFO @ 737839745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 61545122330311823517702908356742064733693623134973698555877656548545484380228 212
UVM_INFO @ 1890249301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 85874476258265423129790813429726054564993484135353365604925107858457289554477 122
UVM_INFO @ 664335494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 91475681228203856080534122138926155292348108743030596243971978444591632470642 240
UVM_INFO @ 1596104208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_stress_all_with_rand_reset 98443780192321938169688193818771968463764111131447708932362268873888379731616 337
UVM_INFO @ 3331546585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 3 test runs
edn_disable_auto_req_mode 97351609105898325374072640504826224679184540637263628437637017566590358586685 88
UVM_INFO @ 13666812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 11752599363020575128016445582405190456162294534474576824566894066414922655731 88
UVM_INFO @ 19755206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
edn_disable_auto_req_mode 75767091014261601985366600410297109476142432552349840602484034452533597590818 88
UVM_INFO @ 19917954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCIBH] Illegal bin hit 1 test run
edn_disable_auto_req_mode 37233530296025564177778777962366327875027959049770642899371385358806125185978 91
/nightly/current_run/scratch/master/edn_edn1-sim-vcs/default/fusesoc-work/src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv, 25
csrng_agent_pkg, "csrng_agent_pkg::device_cmd_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 45280372 ps, Illegal
state bin il of coverpoint csrng_cmd_cp in covergroup
UVM_ERROR (edn_scoreboard.sv:318) [scoreboard] Check failed sw_cmd_sts == item.d_data (* [*] vs * [*]) reg name: edn_reg_block.sw_cmd_sts 1 test run
edn_stress_all_with_rand_reset 34207868699212470754182040921813328259731697115418736453145213817253100644171 226
UVM_INFO @ 1655061583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---