Simulation Results: flash_ctrl

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.04 %
  • code
  • 95.78 %
  • assert
  • 97.01 %
  • func
  • 98.33 %
  • line
  • 96.10 %
  • branch
  • 97.45 %
  • cond
  • 94.84 %
  • toggle
  • 98.66 %
  • FSM
  • 91.84 %
Validation stages
V1
100.00%
V2
99.04%
V2S
98.97%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
flash_ctrl_smoke 156.730s 78.285us 50 50 100.00
smoke_hw 5 5 100.00
flash_ctrl_smoke_hw 22.860s 18.368us 5 5 100.00
csr_hw_reset 5 5 100.00
flash_ctrl_csr_hw_reset 45.000s 67.406us 5 5 100.00
csr_rw 20 20 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
csr_bit_bash 5 5 100.00
flash_ctrl_csr_bit_bash 91.330s 6885.659us 5 5 100.00
csr_aliasing 5 5 100.00
flash_ctrl_csr_aliasing 55.970s 1454.171us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 20.090s 44.984us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
flash_ctrl_csr_aliasing 55.970s 1454.171us 5 5 100.00
mem_walk 5 5 100.00
flash_ctrl_mem_walk 13.400s 18.145us 5 5 100.00
mem_partial_access 5 5 100.00
flash_ctrl_mem_partial_access 12.830s 88.156us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 5 5 100.00
flash_ctrl_sw_op 22.050s 22.853us 5 5 100.00
host_read_direct 5 5 100.00
flash_ctrl_host_dir_rd 105.350s 200.326us 5 5 100.00
rma_hw_if 43 43 100.00
flash_ctrl_hw_rma 1456.570s 97855.368us 3 3 100.00
flash_ctrl_hw_rma_reset 1030.410s 350273.129us 20 20 100.00
flash_ctrl_lcmgr_intg 14.130s 24.429us 20 20 100.00
host_controller_arb 5 5 100.00
flash_ctrl_host_ctrl_arb 2081.760s 284590.833us 5 5 100.00
erase_suspend 5 5 100.00
flash_ctrl_erase_suspend 396.080s 30832.394us 5 5 100.00
program_reset 30 30 100.00
flash_ctrl_prog_reset 203.060s 2707.564us 30 30 100.00
full_memory_access 5 5 100.00
flash_ctrl_full_mem_access 2828.510s 2037701.115us 5 5 100.00
rd_buff_eviction 5 5 100.00
flash_ctrl_rd_buff_evict 104.440s 708.163us 5 5 100.00
rd_buff_eviction_w_ecc 97 100 97.00
flash_ctrl_rw_evict 35.160s 44.412us 38 40 95.00
flash_ctrl_rw_evict_all_en 32.500s 81.263us 39 40 97.50
flash_ctrl_re_evict 36.970s 68.579us 20 20 100.00
host_arb 20 20 100.00
flash_ctrl_phy_arb 309.530s 8073.350us 20 20 100.00
host_interleave 20 20 100.00
flash_ctrl_phy_arb 309.530s 8073.350us 20 20 100.00
memory_protection 20 20 100.00
flash_ctrl_mp_regions 929.490s 101009.935us 20 20 100.00
fetch_code 10 10 100.00
flash_ctrl_fetch_code 32.910s 5404.763us 10 10 100.00
all_partitions 20 20 100.00
flash_ctrl_rand_ops 863.030s 453.760us 20 20 100.00
error_mp 10 10 100.00
flash_ctrl_error_mp 670.360s 3704.889us 10 10 100.00
error_prog_win 10 10 100.00
flash_ctrl_error_prog_win 494.200s 12644.383us 10 10 100.00
error_prog_type 5 5 100.00
flash_ctrl_error_prog_type 1461.720s 4315.157us 5 5 100.00
error_read_seed 20 20 100.00
flash_ctrl_hw_read_seed_err 14.460s 23.331us 20 20 100.00
read_write_overflow 4 5 80.00
flash_ctrl_oversize_error 3604.011s 0.000us 4 5 80.00
flash_ctrl_disable 50 50 100.00
flash_ctrl_disable 24.540s 17.297us 50 50 100.00
flash_ctrl_connect 80 80 100.00
flash_ctrl_connect 18.560s 21.216us 80 80 100.00
stress_all 5 5 100.00
flash_ctrl_stress_all 962.960s 5795.981us 5 5 100.00
secret_partition 129 130 99.23
flash_ctrl_hw_sec_otp 188.540s 14685.120us 50 50 100.00
flash_ctrl_otp_reset 126.050s 39.991us 79 80 98.75
isolation_partition 3 3 100.00
flash_ctrl_hw_rma 1456.570s 97855.368us 3 3 100.00
interrupts 97 100 97.00
flash_ctrl_intr_rd 190.020s 3628.817us 39 40 97.50
flash_ctrl_intr_wr 3604.012s 0.000us 9 10 90.00
flash_ctrl_intr_rd_slow_flash 435.510s 246096.394us 40 40 100.00
flash_ctrl_intr_wr_slow_flash 3604.013s 0.000us 9 10 90.00
invalid_op 20 20 100.00
flash_ctrl_invalid_op 73.990s 861.950us 20 20 100.00
mid_op_rst 5 5 100.00
flash_ctrl_mid_op_rst 75.160s 2024.740us 5 5 100.00
double_bit_err 34 35 97.14
flash_ctrl_read_word_sweep_derr 18.450s 46.983us 5 5 100.00
flash_ctrl_ro_derr 136.590s 9684.274us 10 10 100.00
flash_ctrl_rw_derr 223.270s 5226.152us 10 10 100.00
flash_ctrl_derr_detect 227.800s 754.402us 5 5 100.00
flash_ctrl_integrity 538.060s 21206.919us 4 5 80.00
single_bit_err 25 25 100.00
flash_ctrl_read_word_sweep_serr 24.310s 83.451us 5 5 100.00
flash_ctrl_ro_serr 142.890s 2577.691us 10 10 100.00
flash_ctrl_rw_serr 200.110s 19919.858us 10 10 100.00
singlebit_err_counter 5 5 100.00
flash_ctrl_serr_counter 74.550s 3181.899us 5 5 100.00
singlebit_err_address 5 5 100.00
flash_ctrl_serr_address 84.210s 1156.447us 5 5 100.00
scramble 61 62 98.39
flash_ctrl_wo 266.460s 15741.992us 20 20 100.00
flash_ctrl_write_word_sweep 15.280s 150.595us 1 1 100.00
flash_ctrl_read_word_sweep 9.340s 46.337us 1 1 100.00
flash_ctrl_ro 106.410s 1206.626us 20 20 100.00
flash_ctrl_rw 3604.011s 0.000us 19 20 95.00
filesystem_support 5 5 100.00
flash_ctrl_fs_sup 38.690s 1787.168us 5 5 100.00
rma_write_process_error 23 23 100.00
flash_ctrl_rma_err 872.840s 66635.546us 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 136.880s 10032.536us 20 20 100.00
alert_test 50 50 100.00
flash_ctrl_alert_test 14.630s 85.204us 50 50 100.00
intr_test 50 50 100.00
flash_ctrl_intr_test 14.940s 28.269us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
flash_ctrl_tl_errors 20.320s 165.684us 20 20 100.00
tl_d_illegal_access 20 20 100.00
flash_ctrl_tl_errors 20.320s 165.684us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
flash_ctrl_csr_hw_reset 45.000s 67.406us 5 5 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
flash_ctrl_csr_aliasing 55.970s 1454.171us 5 5 100.00
flash_ctrl_same_csr_outstanding 31.540s 874.627us 20 20 100.00
tl_d_partial_access 50 50 100.00
flash_ctrl_csr_hw_reset 45.000s 67.406us 5 5 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
flash_ctrl_csr_aliasing 55.970s 1454.171us 5 5 100.00
flash_ctrl_same_csr_outstanding 31.540s 874.627us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 66.790s 4238.741us 20 20 100.00
tl_intg_err 25 25 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
flash_ctrl_tl_intg_err 621.550s 880.619us 20 20 100.00
sec_cm_reg_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 621.550s 880.619us 20 20 100.00
sec_cm_host_bus_integrity 20 20 100.00
flash_ctrl_tl_intg_err 621.550s 880.619us 20 20 100.00
sec_cm_mem_bus_integrity 6 6 100.00
flash_ctrl_rd_intg 30.070s 63.179us 3 3 100.00
flash_ctrl_wr_intg 14.390s 94.286us 3 3 100.00
sec_cm_scramble_key_sideload 50 50 100.00
flash_ctrl_smoke 156.730s 78.285us 50 50 100.00
sec_cm_lc_ctrl_intersig_mubi 259 260 99.62
flash_ctrl_otp_reset 126.050s 39.991us 79 80 98.75
flash_ctrl_disable 24.540s 17.297us 50 50 100.00
flash_ctrl_sec_info_access 76.730s 2193.075us 50 50 100.00
flash_ctrl_connect 18.560s 21.216us 80 80 100.00
sec_cm_ctrl_config_regwen 5 5 100.00
flash_ctrl_config_regwen 11.680s 71.585us 5 5 100.00
sec_cm_data_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
sec_cm_data_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
sec_cm_info_regions_config_regwen 20 20 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
sec_cm_info_regions_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
sec_cm_bank_config_regwen 20 20 100.00
flash_ctrl_csr_rw 18.700s 79.596us 20 20 100.00
sec_cm_bank_config_shadow 20 20 100.00
flash_ctrl_shadow_reg_errors 99.300s 47.588us 20 20 100.00
sec_cm_mem_ctrl_global_esc 50 50 100.00
flash_ctrl_disable 24.540s 17.297us 50 50 100.00
sec_cm_mem_ctrl_local_esc 6 6 100.00
flash_ctrl_rd_intg 30.070s 63.179us 3 3 100.00
flash_ctrl_access_after_disable 12.820s 39.283us 3 3 100.00
sec_cm_mem_addr_infection 3 3 100.00
flash_ctrl_host_addr_infection 24.550s 64.361us 3 3 100.00
sec_cm_mem_disable_config_mubi 50 50 100.00
flash_ctrl_disable 24.540s 17.297us 50 50 100.00
sec_cm_exec_config_redun 10 10 100.00
flash_ctrl_fetch_code 32.910s 5404.763us 10 10 100.00
sec_cm_mem_scramble 19 20 95.00
flash_ctrl_rw 3604.011s 0.000us 19 20 95.00
sec_cm_mem_integrity 24 25 96.00
flash_ctrl_rw_serr 200.110s 19919.858us 10 10 100.00
flash_ctrl_rw_derr 223.270s 5226.152us 10 10 100.00
flash_ctrl_integrity 538.060s 21206.919us 4 5 80.00
sec_cm_rma_entry_mem_sec_wipe 3 3 100.00
flash_ctrl_hw_rma 1456.570s 97855.368us 3 3 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
sec_cm_phy_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
sec_cm_phy_prog_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
sec_cm_phy_arbiter_ctrl_redun 5 5 100.00
flash_ctrl_phy_arb_redun 25.030s 813.452us 5 5 100.00
sec_cm_phy_host_grant_ctrl_consistency 3 5 60.00
flash_ctrl_phy_host_grant_err 12.830s 5.768us 3 5 60.00
sec_cm_phy_ack_ctrl_consistency 5 5 100.00
flash_ctrl_phy_ack_consistency 14.340s 54.359us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 5 5 100.00
flash_ctrl_sec_cm 2336.360s 1656.995us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 25.450s 132.721us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 3 3 100.00
flash_ctrl_basic_rw 363.410s 606.726us 3 3 100.00

Error Messages

   Test seed line log context
Job timed out after * minutes 4 test runs
flash_ctrl_rw 12671239847572391906713791680845670845745724523189767832775686112094049060346 None
flash_ctrl_oversize_error 56222778696887421471839809099013202423843147020604793154201355208743905210162 None
flash_ctrl_intr_wr 51044810958846368711629753688980663148247877943368613459209405385442128733396 None
flash_ctrl_intr_wr_slow_flash 16956662339477179061292800970401821662291955043400687255127417513538270572495 None
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * 3 test runs
flash_ctrl_integrity 24415421833352006757320296662640043654833876076539619318659323990833402162214 108
UVM_INFO @ 41886223.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict_all_en 100565124115969422989473255777642280380179642337795547907064962090000954938794 108
UVM_INFO @ 80796.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_rw_evict 124038386218502050841135975305144400997481863980956440191363309647985290162 108
UVM_INFO @ 9424.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' 2 test runs
flash_ctrl_phy_host_grant_err 80753968279036363309953338637010592468529328092494145805335162154217331811303 125
UVM_ERROR @ 5767.8 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5767.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
flash_ctrl_phy_host_grant_err 83626565051041824170058176814673268630937902494127286866830330343836526463231 125
UVM_ERROR @ 23236.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 23236.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:376) [rdata_comp_bank1] *: obs:exp *af8c4_7bf6559f:ffffffff_ffffffff mismatch!! 1 test run
flash_ctrl_intr_rd 86125912687462419750460314080290543664452584937895036721779155823663712155208 108
UVM_INFO @ 650509.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * 1 test run
flash_ctrl_rw_evict 13568578602118115084409647519829773671959441279623409411080389373048488967916 108
UVM_INFO @ 12732.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending 'dst_req_o' 1 test run
flash_ctrl_otp_reset 52139421750273447719704858750000706772227903880781424142443194790325836153123 180
UVM_ERROR @ 16477.4 ns: (prim_sync_reqack.sv:355) [ASSERT FAILED] SyncReqAckAckNeedsReq
UVM_INFO @ 16477.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---