Simulation Results: gpio

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.00 %
  • code
  • 98.27 %
  • assert
  • 98.73 %
  • func
  • 100.00 %
  • line
  • 99.76 %
  • branch
  • 99.80 %
  • cond
  • 99.57 %
  • toggle
  • 93.94 %
Validation stages
V1
100.00%
V2
93.28%
V2S
100.00%
V3
42.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 200 200 100.00
gpio_smoke 1.880s 85.938us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.710s 182.034us 50 50 100.00
gpio_smoke_en_cdc_prim 1.980s 223.292us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.590s 136.673us 50 50 100.00
csr_hw_reset 5 5 100.00
gpio_csr_hw_reset 1.000s 16.893us 5 5 100.00
csr_rw 20 20 100.00
gpio_csr_rw 0.990s 12.445us 20 20 100.00
csr_bit_bash 5 5 100.00
gpio_csr_bit_bash 2.780s 846.681us 5 5 100.00
csr_aliasing 5 5 100.00
gpio_csr_aliasing 1.250s 356.796us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
gpio_csr_mem_rw_with_rand_reset 1.540s 25.041us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
gpio_csr_rw 0.990s 12.445us 20 20 100.00
gpio_csr_aliasing 1.250s 356.796us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
direct_and_masked_out 100 100 100.00
gpio_random_dout_din 1.580s 63.389us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.620s 111.920us 50 50 100.00
out_in_regs_read_write 50 50 100.00
gpio_dout_din_regs_random_rw 1.340s 211.919us 50 50 100.00
gpio_interrupt_programming 50 50 100.00
gpio_intr_rand_pgm 1.950s 111.539us 50 50 100.00
random_interrupt_trigger 50 50 100.00
gpio_rand_intr_trigger 3.670s 307.559us 50 50 100.00
interrupt_and_noise_filter 50 50 100.00
gpio_intr_with_filter_rand_intr_event 3.290s 73.392us 50 50 100.00
noise_filter_stress 50 50 100.00
gpio_filter_stress 21.090s 1054.347us 50 50 100.00
regs_long_reads_and_writes 50 50 100.00
gpio_random_long_reg_writes_reg_reads 4.940s 614.977us 50 50 100.00
full_random 50 50 100.00
gpio_full_random 1.500s 199.633us 50 50 100.00
stress_all 5 50 10.00
gpio_stress_all 107.800s 41392.161us 5 50 10.00
alert_test 50 50 100.00
gpio_alert_test 0.950s 15.061us 50 50 100.00
intr_test 50 50 100.00
gpio_intr_test 0.980s 23.023us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
gpio_tl_errors 2.790s 729.161us 20 20 100.00
tl_d_illegal_access 20 20 100.00
gpio_tl_errors 2.790s 729.161us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
gpio_csr_rw 0.990s 12.445us 20 20 100.00
gpio_same_csr_outstanding 1.210s 136.073us 20 20 100.00
gpio_csr_aliasing 1.250s 356.796us 5 5 100.00
gpio_csr_hw_reset 1.000s 16.893us 5 5 100.00
tl_d_partial_access 50 50 100.00
gpio_csr_rw 0.990s 12.445us 20 20 100.00
gpio_same_csr_outstanding 1.210s 136.073us 20 20 100.00
gpio_csr_aliasing 1.250s 356.796us 5 5 100.00
gpio_csr_hw_reset 1.000s 16.893us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
gpio_tl_intg_err 1.800s 689.460us 20 20 100.00
gpio_sec_cm 1.300s 232.821us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
gpio_tl_intg_err 1.800s 689.460us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
straps_data 42 50 84.00
gpio_rand_straps 0.970s 18.205us 42 50 84.00
stress_all_with_rand_reset 0 50 0.00
gpio_stress_all_with_rand_reset 33.580s 3341.015us 0 50 0.00

Error Messages

   Test seed line log context
UVM_ERROR (gpio_scoreboard.sv:216) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 53 test runs
gpio_stress_all 114568386021022302548372310159829180174809010984211398247017857744315741454429 1642
UVM_INFO @ 69896695372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 113321481514889664604162249218336953614497035592375826073037623079192434133952 374
UVM_INFO @ 764070911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 19621870936274444455421241325687597514726041736939047793375662570638032163105 1277
UVM_INFO @ 40201787029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 104618062579234197726420740177822790040717302109462020412356333711699835583821 75
UVM_INFO @ 5763622 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 65137857784243396201008740685854838148429939565053582087767418500774680956217 76
UVM_INFO @ 1074521031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 5640773668012454652483041416301753901707759983010879343227163452279399900141 961
UVM_INFO @ 16885199234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 110179824100692707333926697168442593431917184782184349332125413289806662365610 75
UVM_INFO @ 18748221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 54793947305934844441937613722915106174277960417287171231276787000030704568503 955
UVM_INFO @ 12228999595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12942174720792661076178466189216985875752599292291572764131698098683470820973 821
UVM_INFO @ 10894857945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 26853482227226682801549680274081081990766158335099153133591445978084550389708 661
UVM_INFO @ 2091962499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58669146374220135887827663091660402491488703619649691098461311051615149997165 81
UVM_INFO @ 1796968132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 15959243701993342373247609258305336620769760793581605470034838881559117794910 77
UVM_INFO @ 109443263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 32670942918595887957072262044431703836854551214958620315307699348058018999100 81
UVM_INFO @ 387027951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 110928987661106934339856611344957392604513843357315350010473108972946381888389 225
UVM_INFO @ 2461143026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 33986188158296924274521841561381051058951870313754126557383934414934444252885 2477
UVM_INFO @ 14026514651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 45443666647396962204134443741528790564965729559158271878131828457402048380595 169
UVM_INFO @ 394559609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 2954543252924268028840148831537711977462578401690261628210062620164942706923 509
UVM_INFO @ 593434556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 25395165803162190204526856195029334708442943323225894696614751876082334226154 642
UVM_INFO @ 14200622830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 80822905446361063229223593757251740863195614199078350778231097731273506509155 375
UVM_INFO @ 1541063614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 90334193998462078806399801774490211213690299378014975774352219396122109339115 594
UVM_INFO @ 1956498961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 7990841527856894281857731543169269902091090150348994920351336141908815625987 797
UVM_INFO @ 4552749608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 107150601713322036286082719542681095211810483922999918171471204760902072325455 576
UVM_INFO @ 1882512885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 105649074236669407350264908786896684269905785916087144999320166000747383244695 829
UVM_INFO @ 2128801604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 3146779526041107826052569941129118277309784780647526253470176588268625404518 763
UVM_INFO @ 2634433766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13429966483273829474060467401954277416183600700561178410162723041823871632978 787
UVM_INFO @ 2312090656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 86785853374209225183264920476137839763772521482536250635101505203866279860678 1445
UVM_INFO @ 12486010910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 42227409895055826919222064252026554579939642013689070190680332139623578508041 75
UVM_INFO @ 2171015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 91149516902313689745335543484811511335009360772850078444629353569923698660842 1230
UVM_INFO @ 25458836547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 58689846149168567717362302652346131501202975081045313719203753754040116688662 319
UVM_INFO @ 2155334153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 53241341369606724199046979184142158036644188348247995056061446495411182991822 571
UVM_INFO @ 2529381419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 26828202331876003939427891260081603561215538227869464761604699930205518511990 79
UVM_INFO @ 131384060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 19818015125367263106440045783204857057973142265992271934395099133485660137693 75
UVM_INFO @ 1443916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 5165833744858108235702653639050460848086400871995949397924862047344433210621 2379
UVM_INFO @ 41392160751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 80802730550274199202608440081327976544097984814471670959090510654420305024723 893
UVM_INFO @ 16278531851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 88840939204510228959013895506144299191651662570638720822159906496682850277484 316
UVM_INFO @ 1391099900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 84210959792442328067019632563422831990469244662316467003981938112026629309018 1258
UVM_INFO @ 66991518345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 13760246248455880175302134091840241277259857856385015705399898202418856327257 989
UVM_INFO @ 3086317453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 9814909927946313873658932420605237875987976458772198596915010124944500910321 1908
UVM_INFO @ 47316037456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 100614408747857696746990282027819380410978917592623864637594570991435893332805 910
UVM_INFO @ 1904184956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 65102701349757815274116499036042226876295674181006230306651730435501501917941 75
UVM_INFO @ 2978015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 61706501107008510950293477436285826743928831450310301535943002456210819370009 76
UVM_INFO @ 314900145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 62886769946729986324335432132779805573033704346350810584983613335424456721987 1477
UVM_INFO @ 7627885407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 47896149808535247471705131924006557257400349013969477034581734381748178605929 2452
UVM_INFO @ 35377921209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 76107104303132474260770008093485546205046676423687437004900671796987447827118 75
UVM_INFO @ 972654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 696652219138503461642271318165265859182844559695004665566184373580452668456 79
UVM_INFO @ 163912346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 63847424242744594634451979319994050668320752160278311949465356844381736005616 75
UVM_INFO @ 7504900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 11303518547480569157930222884655908925302290559670219656908118251538181421440 945
UVM_INFO @ 3341073246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_rand_straps 58805772635932277529849796320857106302254983317274634514579802283533943112627 75
UVM_INFO @ 11471909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 12197571931393603722824381174531014089380062760319031584709077866511906562836 270
UVM_INFO @ 3475555652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 64527468993011105680646279667738423701843785822443396828627759561162327249729 86
UVM_INFO @ 651535848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 30133631713969105270351538801294780486898362772537259140404567805001697841687 405
UVM_INFO @ 3457688371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 79509371161789166684371331475861239287061085877709299963562410101065522248097 1296
UVM_INFO @ 1895506974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all 88789372336331878608440349052593988760553383563796120374414235317402825549922 77
UVM_INFO @ 75663150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [gpio_common_vseq] Check failed (vseq_done) 30 test runs
gpio_stress_all_with_rand_reset 60147439050658694206362899107903088575340298511328663822234299726604435765467 122
UVM_INFO @ 4373861969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 90226734433031198516394766976811879414332875450849938110966566923102443279282 350
UVM_INFO @ 583061620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 74928876582143376285537030302443752290140580685296224382754915572696173299620 162
UVM_INFO @ 493796716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 113114719622021129762644803731072929211489129703413069754175181349161645521462 105
UVM_INFO @ 724328715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17683843616946778958398554320211818825288013267797720218293704120679212513139 265
UVM_INFO @ 140561220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 15309502629772985211557722650363868016111183790918651729436537737371116636091 188
UVM_INFO @ 7887066812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 5474750633699925216458006104593122495084858840777187412844042031365961487337 80
UVM_INFO @ 199893688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 100296419241295986331698375157703728087827406234580946542123701668096739684911 190
UVM_INFO @ 841295013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 18775741904694246683981325052889849817123158923194526121736228291932245624529 80
UVM_INFO @ 15844577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 434628787856205085061463912188785244792722391091088894611710092409664066483 84
UVM_INFO @ 995705846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6548824586140765044431391923741603188369476832676296191564747589299158137008 138
UVM_INFO @ 191239837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 507398223657735588588172001966440526408698984379475488776245785891702313511 80
UVM_INFO @ 43226465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 41154906924720935531832318027876491278876527591123684406349000699156561563467 223
UVM_INFO @ 314667612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 8016241349420052816858557939164111962273894400120205311097098623509203240001 80
UVM_INFO @ 119838788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 55586433240615405108363130865521181645049635465721790468640359101534735891040 83
UVM_INFO @ 238487034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 56199300423492491058230406684607559075179428966896275009477883185125301091342 80
UVM_INFO @ 176971999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 73535660683312999436763189469812119612105947794537828888307414892147307994179 171
UVM_INFO @ 1470305923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 9277022125067391609607835935522994956133837777098660491157070408742011728021 80
UVM_INFO @ 12773195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 60946877268302486943022564476334091060295446928819230100855186022538404513631 80
UVM_INFO @ 10155867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 112441446243241789644950879205630075238271157275486136766274777366474164881633 294
UVM_INFO @ 1538498687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 35610777804084894906327358883868155288743901147987252133090501255385684333426 80
UVM_INFO @ 5353768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 64033753064422726995694432990882138615944162485793830614463780923078657086885 87
UVM_INFO @ 26152435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 64243999321135054586797554268711403226337092657559028329361360160690191904736 80
UVM_INFO @ 11699310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 11712646270205015127511921304010353205364535709108323706912039365374494877077 81
UVM_INFO @ 128913771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39522504186629824891034399845267159110125246147744029737911172042878411703970 80
UVM_INFO @ 12465342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 37848726356183946286724607696679974458697372031716080514413288256787801663936 85
UVM_INFO @ 1327165411 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 51742474662020629834275015053755202629086128941168591968770428406395939776152 171
UVM_INFO @ 1785647380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 21701975833150437747576354231379017415342989186110978804886217622074251513965 80
UVM_INFO @ 3682639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 109627639405079714282966073933359411479519142894457884811635653024398124897154 89
UVM_INFO @ 25422699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 58864308872501944233343584455955113701873008351863179827060592454308973771527 537
UVM_INFO @ 3341014908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 20 test runs
gpio_stress_all_with_rand_reset 101205774304093384796531455812795349871224314606373101954258725045626256148641 80
UVM_INFO @ 982484546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 39103967873290584897073609577136766879857076672110179944042213406580331349118 82
UVM_INFO @ 43968064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 97747053544571537577385336845376300552577185032146674167038472676725612345835 78
UVM_INFO @ 156322057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 103041385390976146309073646474295591876372341066443505807628417697975698052506 79
UVM_INFO @ 786955859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 111056641756220133619124357450625878341727847378976938189825579383955886756689 78
UVM_INFO @ 1549670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 29694919920857112269748233379279122714522253921730901299668999850498652194994 78
UVM_INFO @ 1310809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 6972562109857488789638808034494642475779433962301930260445584254590038235153 78
UVM_INFO @ 312778830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 45941773174798832015189456863071675373169091533285430139552245480844673497646 340
UVM_INFO @ 3263706875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 88915320088286988294491288648552871847510631693422754375321695123354733743340 589
UVM_INFO @ 804135394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 75630126698775298395818749787915283921469079577800033987391309107990672440193 79
UVM_INFO @ 444211434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 52888845151756635615353527348471212917265515042306948455294693293977650365920 78
UVM_INFO @ 9627048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 32338396047430830093572758845743274370509763839181767399916683614247206119779 83
UVM_INFO @ 698697970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 57711755584666071013733613906575452965895780645322058597478262073037495592366 80
UVM_INFO @ 11120750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 106655854676419464096541743506684611229762793453534391627791631004839560056866 186
UVM_INFO @ 3777189004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 85364412570235718406495824110156710226132505556087467153358919966684086768867 80
UVM_INFO @ 277138261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 17852274593938265131915862556715163629558400700370769083711414916184681833680 79
UVM_INFO @ 475518733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 20363235282041660654576596676448337142059541202397598155098851340423546760258 78
UVM_INFO @ 2641424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 23018394753162640311940156294385595914340812311846868190254743766743095327188 78
UVM_INFO @ 10927670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 10047405702623554419145078107375942261069984465272806390937937047577606907866 81
UVM_INFO @ 475804542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
gpio_stress_all_with_rand_reset 4623313764363955075829625682545440121064057613234436012754740210618892971988 84
UVM_INFO @ 551096558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---