Simulation Results: hmac

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 99.46 %
  • code
  • 99.31 %
  • assert
  • 99.12 %
  • func
  • 99.95 %
  • line
  • 99.90 %
  • branch
  • 99.83 %
  • cond
  • 96.80 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 15.520s 1678.887us 10 10 100.00
csr_hw_reset 5 5 100.00
hmac_csr_hw_reset 1.300s 36.491us 5 5 100.00
csr_rw 20 20 100.00
hmac_csr_rw 1.300s 70.469us 20 20 100.00
csr_bit_bash 5 5 100.00
hmac_csr_bit_bash 14.260s 642.285us 5 5 100.00
csr_aliasing 5 5 100.00
hmac_csr_aliasing 7.000s 152.786us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
hmac_csr_mem_rw_with_rand_reset 869.160s 486384.926us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
hmac_csr_rw 1.300s 70.469us 20 20 100.00
hmac_csr_aliasing 7.000s 152.786us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 73.270s 1622.314us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 91.360s 6394.463us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 241.220s 7054.956us 30 30 100.00
hmac_test_sha384_vectors 548.130s 128069.095us 75 75 100.00
hmac_test_sha512_vectors 569.120s 16948.167us 75 75 100.00
hmac_test_hmac256_vectors 13.050s 1535.671us 50 50 100.00
hmac_test_hmac384_vectors 16.340s 424.781us 60 60 100.00
hmac_test_hmac512_vectors 19.560s 1848.206us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 37.060s 847.208us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 1256.900s 7329.498us 10 10 100.00
error 10 10 100.00
hmac_error 91.290s 2588.375us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 138.220s 14563.370us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 15.520s 1678.887us 10 10 100.00
hmac_long_msg 73.270s 1622.314us 10 10 100.00
hmac_back_pressure 91.360s 6394.463us 25 25 100.00
hmac_datapath_stress 1256.900s 7329.498us 10 10 100.00
hmac_burst_wr 37.060s 847.208us 50 50 100.00
hmac_stress_all 2493.330s 202390.630us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 15.520s 1678.887us 10 10 100.00
hmac_long_msg 73.270s 1622.314us 10 10 100.00
hmac_back_pressure 91.360s 6394.463us 25 25 100.00
hmac_datapath_stress 1256.900s 7329.498us 10 10 100.00
hmac_wipe_secret 138.220s 14563.370us 10 10 100.00
hmac_test_sha256_vectors 241.220s 7054.956us 30 30 100.00
hmac_test_sha384_vectors 548.130s 128069.095us 75 75 100.00
hmac_test_sha512_vectors 569.120s 16948.167us 75 75 100.00
hmac_test_hmac256_vectors 13.050s 1535.671us 50 50 100.00
hmac_test_hmac384_vectors 16.340s 424.781us 60 60 100.00
hmac_test_hmac512_vectors 19.560s 1848.206us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 15.520s 1678.887us 10 10 100.00
hmac_long_msg 73.270s 1622.314us 10 10 100.00
hmac_back_pressure 91.360s 6394.463us 25 25 100.00
hmac_datapath_stress 1256.900s 7329.498us 10 10 100.00
hmac_burst_wr 37.060s 847.208us 50 50 100.00
hmac_error 91.290s 2588.375us 10 10 100.00
hmac_wipe_secret 138.220s 14563.370us 10 10 100.00
hmac_test_sha256_vectors 241.220s 7054.956us 30 30 100.00
hmac_test_sha384_vectors 548.130s 128069.095us 75 75 100.00
hmac_test_sha512_vectors 569.120s 16948.167us 75 75 100.00
hmac_test_hmac256_vectors 13.050s 1535.671us 50 50 100.00
hmac_test_hmac384_vectors 16.340s 424.781us 60 60 100.00
hmac_test_hmac512_vectors 19.560s 1848.206us 75 75 100.00
hmac_stress_all 2493.330s 202390.630us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 2493.330s 202390.630us 50 50 100.00
alert_test 50 50 100.00
hmac_alert_test 0.960s 57.642us 50 50 100.00
intr_test 50 50 100.00
hmac_intr_test 1.000s 56.706us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
hmac_tl_errors 4.340s 869.526us 20 20 100.00
tl_d_illegal_access 20 20 100.00
hmac_tl_errors 4.340s 869.526us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
hmac_csr_hw_reset 1.300s 36.491us 5 5 100.00
hmac_csr_rw 1.300s 70.469us 20 20 100.00
hmac_csr_aliasing 7.000s 152.786us 5 5 100.00
hmac_same_csr_outstanding 2.980s 143.403us 20 20 100.00
tl_d_partial_access 50 50 100.00
hmac_csr_hw_reset 1.300s 36.491us 5 5 100.00
hmac_csr_rw 1.300s 70.469us 20 20 100.00
hmac_csr_aliasing 7.000s 152.786us 5 5 100.00
hmac_same_csr_outstanding 2.980s 143.403us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 25 25 100.00
hmac_sec_cm 1.400s 538.886us 5 5 100.00
hmac_tl_intg_err 4.610s 1883.641us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
hmac_tl_intg_err 4.610s 1883.641us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 15.520s 1678.887us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 5.650s 122.260us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 719.070s 25990.997us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.050s 249.042us 1 1 100.00