Simulation Results: keymgr

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.94 %
  • code
  • 99.00 %
  • assert
  • 97.72 %
  • func
  • 91.11 %
  • line
  • 99.20 %
  • branch
  • 99.00 %
  • cond
  • 98.16 %
  • toggle
  • 98.63 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.35%
V2S
99.48%
V3
48.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
keymgr_smoke 7.740s 945.913us 50 50 100.00
random 50 50 100.00
keymgr_random 42.730s 5779.170us 50 50 100.00
csr_hw_reset 5 5 100.00
keymgr_csr_hw_reset 1.320s 15.485us 5 5 100.00
csr_rw 20 20 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
csr_bit_bash 5 5 100.00
keymgr_csr_bit_bash 10.810s 4529.754us 5 5 100.00
csr_aliasing 5 5 100.00
keymgr_csr_aliasing 9.280s 1753.690us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
keymgr_csr_mem_rw_with_rand_reset 2.710s 126.071us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
keymgr_csr_aliasing 9.280s 1753.690us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 49 50 98.00
keymgr_cfg_regwen 95.550s 2574.372us 49 50 98.00
sideload 199 200 99.50
keymgr_sideload 28.700s 8123.607us 50 50 100.00
keymgr_sideload_kmac 28.400s 1109.076us 49 50 98.00
keymgr_sideload_aes 52.730s 6217.067us 50 50 100.00
keymgr_sideload_otbn 13.560s 2700.940us 50 50 100.00
direct_to_disabled_state 50 50 100.00
keymgr_direct_to_disabled 11.430s 685.128us 50 50 100.00
lc_disable 49 50 98.00
keymgr_lc_disable 8.820s 4770.430us 49 50 98.00
kmac_error_response 50 50 100.00
keymgr_kmac_rsp_err 5.640s 650.764us 50 50 100.00
invalid_sw_input 50 50 100.00
keymgr_sw_invalid_input 53.480s 2432.610us 50 50 100.00
invalid_hw_input 50 50 100.00
keymgr_hwsw_invalid_input 65.860s 9412.181us 50 50 100.00
sync_async_fault_cross 49 50 98.00
keymgr_sync_async_fault_cross 11.600s 1430.922us 49 50 98.00
stress_all 49 50 98.00
keymgr_stress_all 102.610s 23590.583us 49 50 98.00
intr_test 50 50 100.00
keymgr_intr_test 1.230s 15.980us 50 50 100.00
alert_test 50 50 100.00
keymgr_alert_test 1.300s 43.926us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
keymgr_tl_errors 4.650s 1139.089us 20 20 100.00
tl_d_illegal_access 20 20 100.00
keymgr_tl_errors 4.650s 1139.089us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
keymgr_csr_hw_reset 1.320s 15.485us 5 5 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
keymgr_csr_aliasing 9.280s 1753.690us 5 5 100.00
keymgr_same_csr_outstanding 4.630s 118.781us 20 20 100.00
tl_d_partial_access 50 50 100.00
keymgr_csr_hw_reset 1.320s 15.485us 5 5 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
keymgr_csr_aliasing 9.280s 1753.690us 5 5 100.00
keymgr_same_csr_outstanding 4.630s 118.781us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
tl_intg_err 25 25 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
keymgr_tl_intg_err 7.150s 244.463us 20 20 100.00
shadow_reg_update_error 20 20 100.00
keymgr_shadow_reg_errors 6.100s 244.917us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_shadow_reg_errors 6.100s 244.917us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_shadow_reg_errors 6.100s 244.917us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_shadow_reg_errors 6.100s 244.917us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_shadow_reg_errors_with_csr_rw 16.490s 2727.109us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_bus_integrity 20 20 100.00
keymgr_tl_intg_err 7.150s 244.463us 20 20 100.00
sec_cm_config_shadow 20 20 100.00
keymgr_shadow_reg_errors 6.100s 244.917us 20 20 100.00
sec_cm_op_config_regwen 49 50 98.00
keymgr_cfg_regwen 95.550s 2574.372us 49 50 98.00
sec_cm_reseed_config_regwen 70 70 100.00
keymgr_random 42.730s 5779.170us 50 50 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
sec_cm_sw_binding_config_regwen 70 70 100.00
keymgr_random 42.730s 5779.170us 50 50 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
sec_cm_max_key_ver_config_regwen 70 70 100.00
keymgr_random 42.730s 5779.170us 50 50 100.00
keymgr_csr_rw 1.680s 21.223us 20 20 100.00
sec_cm_lc_ctrl_intersig_mubi 49 50 98.00
keymgr_lc_disable 8.820s 4770.430us 49 50 98.00
sec_cm_constants_consistency 50 50 100.00
keymgr_hwsw_invalid_input 65.860s 9412.181us 50 50 100.00
sec_cm_intersig_consistency 50 50 100.00
keymgr_hwsw_invalid_input 65.860s 9412.181us 50 50 100.00
sec_cm_hw_key_sw_noaccess 50 50 100.00
keymgr_random 42.730s 5779.170us 50 50 100.00
sec_cm_output_keys_ctrl_redun 50 50 100.00
keymgr_sideload_protect 9.930s 598.270us 50 50 100.00
sec_cm_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_data_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_ctrl_fsm_local_esc 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_ctrl_fsm_consistency 50 50 100.00
keymgr_custom_cm 24.860s 1118.877us 50 50 100.00
sec_cm_ctrl_fsm_global_esc 49 50 98.00
keymgr_lc_disable 8.820s 4770.430us 49 50 98.00
sec_cm_ctrl_ctr_redun 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_kmac_if_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_kmac_if_ctr_redun 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 50 50 100.00
keymgr_custom_cm 24.860s 1118.877us 50 50 100.00
sec_cm_kmac_if_done_ctrl_consistency 50 50 100.00
keymgr_custom_cm 24.860s 1118.877us 50 50 100.00
sec_cm_reseed_ctr_redun 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_side_load_sel_ctrl_consistency 50 50 100.00
keymgr_custom_cm 24.860s 1118.877us 50 50 100.00
sec_cm_sideload_ctrl_fsm_sparse 5 5 100.00
keymgr_sec_cm 15.950s 659.272us 5 5 100.00
sec_cm_ctrl_key_integrity 50 50 100.00
keymgr_custom_cm 24.860s 1118.877us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 24 50 48.00
keymgr_stress_all_with_rand_reset 32.390s 3456.642us 24 50 48.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 23 test runs
keymgr_stress_all_with_rand_reset 78193979839026927294780689410211666314029448887133068134516767488839855661756 153
UVM_INFO @ 222822266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87076895289597644842680368035884921931491438331447656518989694434142721865860 146
UVM_INFO @ 255706616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 20656093950395858641198023763769147113220334192524639720202936260347176209602 1673
UVM_INFO @ 1822364399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 703607022155915202674949986684593561432783886230323681118150562107040747419 1680
UVM_INFO @ 2611754598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 38326841283682504306984592570099305283187423495659635042559756867577335404578 128
UVM_INFO @ 415507370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 74652705909961549610627993451753765884475339287754830318221182124114122475612 936
UVM_INFO @ 1821267588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 89387539657205507288107805182622719048525857666926767464858634716478698516381 201
UVM_INFO @ 469028120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 22175753596350573797507434028288172786228987266101897005522328717595070012589 141
UVM_INFO @ 121225085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 39144556960991125854436487552288649607649970843368420217451159678974456958551 107
UVM_INFO @ 632529352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 12312913404978131341227114985314178918479269920435518991860827524263502763780 189
UVM_INFO @ 1514710142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 103645376573742966755262581920248091805955149774655344723755002266423162061803 311
UVM_INFO @ 243207148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 64843900012100658081197064528939208749907395115633978052583740312754018659774 259
UVM_INFO @ 705879687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 32879400758847511755820600246198785502977626833266258393976208825990318207902 455
UVM_INFO @ 692132320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 108475485253808663993333984203544329538312864908482157518442207811012867565207 368
UVM_INFO @ 163372929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 12172966476943560136314532604891175301564080874402059963656703594149406447432 782
UVM_INFO @ 930416999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 66448030131380951932698306633865764539535714012269867071710688968862848108262 249
UVM_INFO @ 362884273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 97954632707730275306228573190847342891600430506112093986928339767869846449854 454
UVM_INFO @ 261825019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 26897058967539980688173202918088050552268062078798552426774996175096805858551 2447
UVM_INFO @ 2766759373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 87764979853921582720835012531507686028863276934250762081712539890848738145083 347
UVM_INFO @ 768067394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 4865992867974489947154291445553807380885411261612108678436009899075984893443 661
UVM_INFO @ 930596505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 5308687776080165423775761555303543602921307598256882320419931706631377262212 101
UVM_INFO @ 118193684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 51169811181289244158684790017614259335737372795720978604970392757044110024863 207
UVM_INFO @ 975441232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_stress_all_with_rand_reset 99886856370812131107776852954087333812627213879345052191180380561610937674338 179
UVM_INFO @ 203673818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data != `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.sw_share1_output_* 2 test runs
keymgr_stress_all_with_rand_reset 53395509265057210512186719314835771166535163413871159627014242158859008106043 908
UVM_INFO @ 367617957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
keymgr_lc_disable 92570932250563535478030822913591280936018846939024755706401291364162863176500 127
UVM_INFO @ 46669016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == `gmv(csr) (* [*] vs * [*]) reg name: keymgr_reg_block.start 1 test run
keymgr_cfg_regwen 24072289577310251564833576701146801138289400046621079141444248492308695678690 172
UVM_INFO @ 7780368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:546) [scoreboard] Check failed item.d_data == addr_phase_cfg_regwen (* [*] vs * [*]) 1 test run
keymgr_stress_all_with_rand_reset 26716384968797262748505451295442489268663261558687603112117903053693397355141 151
UVM_INFO @ 10513997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err is not received! 1 test run
keymgr_sync_async_fault_cross 58555677610623907775053419033605885187279646204515934895900458170489520502689 214
UVM_INFO @ 120986991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) 1 test run
keymgr_stress_all 101656490870013539637856864428560043821194192357647673367527436683795144672760 1961
UVM_INFO @ 263083369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1064) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation 1 test run
keymgr_stress_all_with_rand_reset 64305198207934354583097577798838111497135554290625474767926629173072756814008 777
HardwareRevisionSecret act: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170, exp: 0x69802e51bacf8874e650d692e3d8a6462d3f158f0bf7961dd346f880b4d52170
RomDigest act: 0xadf3b76304fd37740d1207e616cace6e9af10e3086d6411baaf32f769599e5d2, exp: 0xadf3b76304fd37740d1207e616cace6e9af10e3086d6411baaf32f769599e5d2
HealthMeasurement act: 0x1bb387d9dc3e8286b7a715bba380c5b4, exp: 0x1bb387d9dc3e8286b7a715bba380c5b4
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* 1 test run
keymgr_sideload_kmac 85834855049698769091319052038885225912946257212690527863456894777308332605900 85
UVM_INFO @ 25018136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---