Simulation Results: kmac/masked

 
23/05/2026 11:52:00 DVSim: v1.49.0 sha: 21f062e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.99 %
  • code
  • 94.12 %
  • assert
  • 98.85 %
  • func
  • 97.99 %
  • line
  • 99.25 %
  • branch
  • 97.10 %
  • cond
  • 94.78 %
  • toggle
  • 99.89 %
  • FSM
  • 79.58 %
Validation stages
V1
100.00%
V2
99.74%
V2S
99.56%
V3
80.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 50 50 100.00
kmac_smoke 95.260s 26459.486us 50 50 100.00
csr_hw_reset 5 5 100.00
kmac_csr_hw_reset 1.580s 50.721us 5 5 100.00
csr_rw 20 20 100.00
kmac_csr_rw 1.600s 68.447us 20 20 100.00
csr_bit_bash 5 5 100.00
kmac_csr_bit_bash 16.130s 302.591us 5 5 100.00
csr_aliasing 5 5 100.00
kmac_csr_aliasing 9.520s 3392.595us 5 5 100.00
csr_mem_rw_with_rand_reset 20 20 100.00
kmac_csr_mem_rw_with_rand_reset 3.170s 289.463us 20 20 100.00
regwen_csr_and_corresponding_lockable_csr 25 25 100.00
kmac_csr_rw 1.600s 68.447us 20 20 100.00
kmac_csr_aliasing 9.520s 3392.595us 5 5 100.00
mem_walk 5 5 100.00
kmac_mem_walk 1.130s 14.535us 5 5 100.00
mem_partial_access 5 5 100.00
kmac_mem_partial_access 1.930s 136.037us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 50 50 100.00
kmac_long_msg_and_output 4968.310s 142078.725us 50 50 100.00
burst_write 50 50 100.00
kmac_burst_write 1384.800s 78650.006us 50 50 100.00
test_vectors 39 40 97.50
kmac_test_vectors_sha3_224 3004.390s 703540.134us 5 5 100.00
kmac_test_vectors_sha3_256 2538.610s 303142.275us 4 5 80.00
kmac_test_vectors_sha3_384 1994.070s 152447.026us 5 5 100.00
kmac_test_vectors_sha3_512 1327.030s 163066.142us 5 5 100.00
kmac_test_vectors_shake_128 3185.410s 256819.745us 5 5 100.00
kmac_test_vectors_shake_256 2454.090s 233232.908us 5 5 100.00
kmac_test_vectors_kmac 3.220s 883.267us 5 5 100.00
kmac_test_vectors_kmac_xof 3.300s 316.242us 5 5 100.00
sideload 50 50 100.00
kmac_sideload 532.090s 121409.195us 50 50 100.00
app 50 50 100.00
kmac_app 345.980s 157251.781us 50 50 100.00
app_with_partial_data 10 10 100.00
kmac_app_with_partial_data 348.760s 63532.414us 10 10 100.00
entropy_refresh 50 50 100.00
kmac_entropy_refresh 328.130s 18380.923us 50 50 100.00
error 49 50 98.00
kmac_error 448.430s 99921.807us 49 50 98.00
key_error 50 50 100.00
kmac_key_error 15.450s 1887.046us 50 50 100.00
sideload_invalid 50 50 100.00
kmac_sideload_invalid 9.480s 1229.644us 50 50 100.00
edn_timeout_error 20 20 100.00
kmac_edn_timeout_error 51.820s 9826.319us 20 20 100.00
entropy_mode_error 20 20 100.00
kmac_entropy_mode_error 19.050s 1042.247us 20 20 100.00
entropy_ready_error 10 10 100.00
kmac_entropy_ready_error 55.410s 27356.343us 10 10 100.00
lc_escalation 50 50 100.00
kmac_lc_escalation 39.310s 994.071us 50 50 100.00
stress_all 50 50 100.00
kmac_stress_all 3043.610s 96323.559us 50 50 100.00
intr_test 50 50 100.00
kmac_intr_test 1.220s 18.926us 50 50 100.00
alert_test 50 50 100.00
kmac_alert_test 1.340s 172.930us 50 50 100.00
tl_d_oob_addr_access 20 20 100.00
kmac_tl_errors 4.190s 594.618us 20 20 100.00
tl_d_illegal_access 20 20 100.00
kmac_tl_errors 4.190s 594.618us 20 20 100.00
tl_d_outstanding_access 50 50 100.00
kmac_csr_hw_reset 1.580s 50.721us 5 5 100.00
kmac_csr_rw 1.600s 68.447us 20 20 100.00
kmac_csr_aliasing 9.520s 3392.595us 5 5 100.00
kmac_same_csr_outstanding 3.170s 112.588us 20 20 100.00
tl_d_partial_access 50 50 100.00
kmac_csr_hw_reset 1.580s 50.721us 5 5 100.00
kmac_csr_rw 1.600s 68.447us 20 20 100.00
kmac_csr_aliasing 9.520s 3392.595us 5 5 100.00
kmac_same_csr_outstanding 3.170s 112.588us 20 20 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
kmac_shadow_reg_errors 2.690s 357.195us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
kmac_shadow_reg_errors 2.690s 357.195us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
kmac_shadow_reg_errors 2.690s 357.195us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
kmac_shadow_reg_errors 2.690s 357.195us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
kmac_shadow_reg_errors_with_csr_rw 6.590s 499.543us 19 20 95.00
tl_intg_err 25 25 100.00
kmac_sec_cm 112.280s 9221.884us 5 5 100.00
kmac_tl_intg_err 5.820s 209.999us 20 20 100.00
sec_cm_bus_integrity 20 20 100.00
kmac_tl_intg_err 5.820s 209.999us 20 20 100.00
sec_cm_lc_escalate_en_intersig_mubi 50 50 100.00
kmac_lc_escalation 39.310s 994.071us 50 50 100.00
sec_cm_sw_key_key_masking 50 50 100.00
kmac_smoke 95.260s 26459.486us 50 50 100.00
sec_cm_key_sideload 50 50 100.00
kmac_sideload 532.090s 121409.195us 50 50 100.00
sec_cm_cfg_shadowed_config_shadow 20 20 100.00
kmac_shadow_reg_errors 2.690s 357.195us 20 20 100.00
sec_cm_fsm_sparse 5 5 100.00
kmac_sec_cm 112.280s 9221.884us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
kmac_sec_cm 112.280s 9221.884us 5 5 100.00
sec_cm_packer_ctr_redun 5 5 100.00
kmac_sec_cm 112.280s 9221.884us 5 5 100.00
sec_cm_cfg_shadowed_config_regwen 50 50 100.00
kmac_smoke 95.260s 26459.486us 50 50 100.00
sec_cm_fsm_global_esc 50 50 100.00
kmac_lc_escalation 39.310s 994.071us 50 50 100.00
sec_cm_fsm_local_esc 5 5 100.00
kmac_sec_cm 112.280s 9221.884us 5 5 100.00
sec_cm_absorbed_ctrl_mubi 10 10 100.00
kmac_mubi 312.540s 23230.062us 10 10 100.00
sec_cm_sw_cmd_ctrl_sparse 50 50 100.00
kmac_smoke 95.260s 26459.486us 50 50 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 10 80.00
kmac_stress_all_with_rand_reset 279.280s 3929.844us 8 10 80.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:858) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) 2 test runs
kmac_stress_all_with_rand_reset 52927369096408540633776531493661928249915453217426830917528960571865332777045 342
UVM_INFO @ 6644350850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 64393252540814069516939002540913078669715238693315754899417664906536978807514 243
UVM_INFO @ 2220177734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 1 test run
kmac_test_vectors_sha3_256 89559503206297206289094071151042730789878843873726919469047163379812542595056 78
UVM_INFO @ 23606432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: * 1 test run
kmac_shadow_reg_errors_with_csr_rw 30163896474466193950124184528853238512974413008128935298923149060912920278185 341
UVM_INFO @ 179460198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
kmac_error 86235858235813212290431786502665280999798311160082869011243215562875161544258 198
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---